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csr regfile: force mstatus.UBE to 0 (see #1417) (#1626)

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as CVA6 is little endian

Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
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André Sintzoff 2023-11-14 13:28:20 +01:00 • committed by GitHub
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core/csr_regfile.sv
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@ -789,6 +789,7 @@ module csr_regfile
mstatus_d.wpri1 = 1'b0; mstatus_d.wpri1 = 1'b0;
mstatus_d.wpri2 = 1'b0; mstatus_d.wpri2 = 1'b0;
mstatus_d.wpri0 = 1'b0; mstatus_d.wpri0 = 1'b0;
mstatus_d.ube = 1'b0; // CVA6 is little-endian
// this register has side-effects on other registers, flush the pipeline // this register has side-effects on other registers, flush the pipeline
flush_o = 1'b1; flush_o = 1'b1;
end end