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📝 Add some comments in port definitions

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This commit is contained in:
Florian Zaruba 2017-06-03 17:55:39 +02:00
parent d946c1491d
commit 07335ff2c8
2 changed files with 32 additions and 32 deletions
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24
src/controller.sv
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@ -20,20 +20,20 @@
import ariane_pkg::*;
module controller (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
output logic flush_bp_o, // flush branch prediction data structures
output logic flush_pcgen_o, // flush PC Generation Stage
output logic flush_if_o, // flush the IF stage
output logic flush_unissued_instr_o, // flush un-issued instructions of the scoreboard
output logic flush_id_o, // flush ID stage
output logic flush_ex_o, // flush EX stage
output logic flush_bp_o, // Flush branch prediction data structures
output logic flush_pcgen_o, // Flush PC Generation Stage
output logic flush_if_o, // Flush the IF stage
output logic flush_unissued_instr_o, // Flush un-issued instructions of the scoreboard
output logic flush_id_o, // Flush ID stage
output logic flush_ex_o, // Flush EX stage
input logic eret_i, // return from exception
input exception ex_i, // we got an exception, flush the pipeline
input branchpredict resolved_branch_i, // we got a resolved branch, check if we need to flush the front-end
input logic flush_csr_i // we got an instruction which altered the CSR, flush the pipeline
input logic eret_i, // Return from exception
input exception ex_i, // We got an exception, flush the pipeline
input branchpredict resolved_branch_i, // We got a resolved branch, check if we need to flush the front-end
input logic flush_csr_i // We got an instruction which altered the CSR, flush the pipeline
);
// flush branch prediction
assign flush_bp_o = 1'b0;

40
src/csr_regfile.sv
View file

@ -24,32 +24,32 @@ module csr_regfile #(
)(
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
// send a flush request out if a CSR with a side effect has changed
// send a flush request out if a CSR with a side effect has changed (e.g. written)
output logic flush_o,
// Core and Cluster ID
input logic [3:0] core_id_i,
input logic [5:0] cluster_id_i,
input logic [63:0] boot_addr_i,
input logic [3:0] core_id_i, // Core ID is considered static
input logic [5:0] cluster_id_i, // Cluster ID is considered static
input logic [63:0] boot_addr_i, // Address from which to start booting, mtvec is set to the same address
// we are taking an exception
input exception ex_i,
input exception ex_i, // We've got an exception from the commit stage, take its
input fu_op csr_op_i,
input logic [11:0] csr_addr_i,
input logic [63:0] csr_wdata_i,
output logic [63:0] csr_rdata_o,
input logic [63:0] pc_i, // PC of instruction accessing the CSR
output exception csr_exception_o, // attempts to access a CSR without appropriate privilege
// level or to write a read-only register also
// raises illegal instruction exceptions.
input fu_op csr_op_i, // Operation to perform on the CSR file
input logic [11:0] csr_addr_i, // Address of the register to read/write
input logic [63:0] csr_wdata_i, // Write data in
output logic [63:0] csr_rdata_o, // Read data out
input logic [63:0] pc_i, // PC of instruction accessing the CSR
output exception csr_exception_o, // attempts to access a CSR without appropriate privilege
// level or to write a read-only register also
// raises illegal instruction exceptions.
// Interrupts/Exceptions
output logic [3:0] irq_enable_o,
output logic [63:0] epc_o,
output logic eret_o, // return from exception
output logic [63:0] trap_vector_base_o,
output priv_lvl_t priv_lvl_o,
output logic [3:0] irq_enable_o, // Directly output the interrupt enable flag
output logic [63:0] epc_o, // Output the exception PC to PC Gen, the correct CSR (mepc, sepc) is set accordingly
output logic eret_o, // Return from exception, set the PC of epc_o
output logic [63:0] trap_vector_base_o, // Output base of exception vector, correct CSR is output (mtvec, stvec)
output priv_lvl_t priv_lvl_o, // Current privilege level the CPU is in
// MMU
output logic enable_translation_o,
output logic flag_pum_o,
output logic enable_translation_o, // Enable VA translation
output logic flag_pum_o, // TODO: this is called SUM now
output logic flag_mxr_o,
// input logic flag_mprv_i,
output logic [37:0] pd_ppn_o,