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Fix single-stepping
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parent
257d017abb
commit
082ab36a03
2 changed files with 16 additions and 6 deletions
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@ -542,9 +542,21 @@ module csr_regfile #(
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end
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// single step enable and we just retired an instruction
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if (dcsr_q.step && (|commit_ack_i)) begin
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// we saved the correct target address during execute
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dpc_d = commit_instr_i[0].bp.predict_address;
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if (dcsr_q.step && commit_ack_i[0]) begin
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// valid CTRL flow change
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if (commit_instr_i[0].fu == CTRL_FLOW) begin
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// we saved the correct target address during execute
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dpc_d = commit_instr_i[0].bp.predict_address;
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// exception valid
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end else if (ex_i.valid) begin
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dpc_d = trap_vector_base_o;
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// return from environment
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end else if (eret_o) begin
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dpc_d = epc_o;
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// consecutive PC
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end else begin
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dpc_d = commit_instr_i[0].pc + (commit_instr_i[0].is_compressed ? 'h2 : 'h4);
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end
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debug_mode_d = 1'b1;
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set_debug_pc_o = 1'b1;
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dcsr_d.cause = dm::CauseSingleStep;
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@ -124,9 +124,7 @@ module scoreboard #(
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mem_n[trans_id_i[i]].sbe.valid = 1'b1;
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mem_n[trans_id_i[i]].sbe.result = wbdata_i[i];
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// save the target address of a branch (needed for debug in commit stage)
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if (resolved_branch_i.valid) begin
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mem_n[trans_id_i[i]].sbe.bp.predict_address = resolved_branch_i.target_address;
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end
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mem_n[trans_id_i[i]].sbe.bp.predict_address = resolved_branch_i.target_address;
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// write the exception back if it is valid
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if (ex_i[i].valid) begin
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mem_n[trans_id_i[i]].sbe.ex = ex_i[i];
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