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Implement dcache bypass mode [ci skip]
This commit is contained in:
Florian Zaruba
parent
107cd30a9d
commit
10f47425fb
10 changed files with 484 additions and 211 deletions
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@ -16,8 +16,17 @@ package nbdcache_pkg;
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typedef struct packed {
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logic valid;
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miss_t type;
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miss_t req_type;
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logic [55:0] addr;
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} mshr_t;
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typedef struct packed {
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logic valid;
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logic bypass;
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logic [63:0] addr;
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logic [7:0] be;
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logic we;
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logic [63:0] wdata;
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} miss_req_t;
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endpackage
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@ -55,6 +55,7 @@ module ariane
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input logic [63:0] instr_if_data_rdata_i,
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// Data memory interface
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AXI_BUS.Master data_if,
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AXI_BUS.Master bypass_if,
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// Interrupt inputs
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input logic irq_i, // level sensitive IR lines
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input logic [4:0] irq_id_i,
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@ -172,7 +172,7 @@ module axi_adapter #(
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axi.aw_valid = 1'b1;
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axi.aw_len = 8'b0;
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if (axi.aw_read)
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if (axi.aw_ready)
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state_d = WAIT_B_VALID;
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end
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@ -7,10 +7,171 @@
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*
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* Description: Cache controller
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*/
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module cache_ctrl (
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input logic clk_i, // Clock
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input logic rst_ni // Asynchronous reset active low
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import ariane_pkg::*;
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import nbdcache_pkg::*;
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module cache_ctrl #(
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parameter int unsigned SET_ASSOCIATIVITY = 8,
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parameter int unsigned INDEX_WIDTH = 12,
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parameter int unsigned TAG_WIDTH = 44,
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parameter int unsigned CACHE_LINE_WIDTH = 100
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)(
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input logic clk_i, // Clock
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input logic rst_ni, // Asynchronous reset active low
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input logic bypass_i, // enable cache
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// Core request ports
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input logic [INDEX_WIDTH-1:0] address_index_i,
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input logic [TAG_WIDTH-1:0] address_tag_i,
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input logic [63:0] data_wdata_i,
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input logic data_req_i,
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input logic data_we_i,
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input logic [7:0] data_be_i,
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input logic kill_req_i,
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input logic tag_valid_i,
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output logic data_gnt_o,
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output logic data_rvalid_o,
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output logic [63:0] data_rdata_o,
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input amo_t amo_op_i,
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// SRAM interface, read only
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output logic [SET_ASSOCIATIVITY-1:0] req_o, // req is valid
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output logic [SET_ASSOCIATIVITY-1:0][INDEX_WIDTH-1:0] adrr_o, // address into cache array
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input logic [SET_ASSOCIATIVITY-1:0][CACHE_LINE_WIDTH-1:0] tag_i,
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input logic [SET_ASSOCIATIVITY-1:0][TAG_WIDTH-1:0] data_i,
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output logic [SET_ASSOCIATIVITY-1:0] we_o,
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// Miss handling
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output miss_req_t miss_req_o,
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// return
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input logic miss_gnt_i,
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input logic miss_valid_i,
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input logic [63:0] miss_data_i,
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// check MSHR for aliasing
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output logic [63:0] mshr_addr_o,
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input logic mashr_addr_matches_i
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);
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enum logic [2:0] {
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IDLE, WAIT_TAG, WAIT_TAG_BYPASSED, WAIT_REFILL_VALID, WAIT_REFILL_GNT
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} state_d, state_q;
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typedef struct packed {
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logic [INDEX_WIDTH-1:0] index;
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logic [TAG_WIDTH-1:0] tag;
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logic [7:0] be;
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logic we;
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logic bypass;
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} mem_req_t;
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mem_req_t mem_req_d, mem_req_q;
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// --------------
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// Cache FSM
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// --------------
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always_comb begin : cache_ctrl_fsm
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// default assignments
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state_d = state_q;
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mem_req_d = mem_req_q;
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// output assignments
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data_gnt_o = 1'b0;
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data_rvalid_o = 1'b0;
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data_rdata_o = '0;
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miss_req_o = '0;
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case (state_q)
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IDLE: begin
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// a new request arrived
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if (data_req_i) begin
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// Bypass mode, check for uncacheable address here as well
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if (bypass_i) begin
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state_d = WAIT_TAG_BYPASSED;
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// grant this access
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data_gnt_o = 1'b1;
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// save index, be and we
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mem_req_d = { address_index_i, mem_req_q.tag, data_be_i, data_we_i, data_wdata_i, 1'b1};
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// ------------------
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// Cache is enabled
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// ------------------
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end else begin
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end
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end
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end
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// cache enabled and waiting for tag
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WAIT_TAG: begin
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// HIT CASE
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// MISS CASE
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end
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// its for sure a miss
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WAIT_TAG_BYPASSED: begin
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// the request was killed
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if (kill_req_i)
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state_d = IDLE;
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else begin
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// save tag
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mem_req_d.tag = address_tag_i;
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// make request to miss unit
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miss_req_o = { 1'b1, mem_req_d.bypass, address_tag_i, mem_req_q.index, mem_req_q.be, mem_req_q.we };
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// wait for the grant
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if (!miss_gnt_i)
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state_d = WAIT_REFILL_GNT;
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else
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state_d = WAIT_REFILL_VALID;
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end
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end
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// ~> wait for grant from miss unit
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WAIT_REFILL_GNT: begin
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miss_req_o = {1'b1, mem_req_q.bypass, mem_req_q.tag, mem_req_q.index, mem_req_q.be, mem_req_q.we };
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// got a grant so go to valid
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if (miss_gnt_i)
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state_d = WAIT_REFILL_VALID;
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end
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WAIT_REFILL_VALID: begin
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// got a valid answer
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if (miss_valid_i) begin
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data_rdata_o = miss_data_i;
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data_rvalid_o = 1'b1;
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state_d = IDLE;
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end
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end
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endcase
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end
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// --------------
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// Registers
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// --------------
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if(~rst_ni) begin
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state_q <= IDLE;
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mem_req_q <= '0;
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end else begin
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state_q <= state_d;
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mem_req_q <= mem_req_d;
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end
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end
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endmodule
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module AMO_alu (
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input logic clk_i,
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input logic rst_ni,
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// AMO interface
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input logic amo_commit_i, // commit atomic memory operation
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output logic amo_valid_o, // we have a valid AMO result
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output logic [63:0] amo_result_o, // result of atomic memory operation
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input logic amo_flush_i // forget about AMO
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);
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endmodule
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@ -1,193 +0,0 @@
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// Author: Florian Zaruba, ETH Zurich
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// Date: 24.4.2017
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// Description: Arbitrates the dcache ports
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//
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//
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// Copyright (C) 2017 ETH Zurich, University of Bologna
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// All rights reserved.
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//
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// This code is under development and not yet released to the public.
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// Until it is released, the code is under the copyright of ETH Zurich and
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// the University of Bologna, and may contain confidential and/or unpublished
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// work. Any reuse/redistribution is strictly forbidden without written
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// permission from ETH Zurich.
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//
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// Bug fixes and contributions will eventually be released under the
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// SolderPad open hardware license in the context of the PULP platform
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// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the
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// University of Bologna.
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//
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import ariane_pkg::*;
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module dcache_arbiter #(
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parameter int NR_PORTS = 3
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)
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(
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input logic clk_i, // Clock
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input logic rst_ni, // Asynchronous reset active low
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// slave port
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output logic [11:0] address_index_o,
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output logic [43:0] address_tag_o,
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output logic [63:0] data_wdata_o,
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output logic data_req_o,
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output logic data_we_o,
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output logic [7:0] data_be_o,
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output logic kill_req_o,
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output logic tag_valid_o,
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input logic data_gnt_i,
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input logic data_rvalid_i,
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input logic [63:0] data_rdata_i,
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// master ports
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input logic [NR_PORTS-1:0][11:0] address_index_i,
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input logic [NR_PORTS-1:0][43:0] address_tag_i,
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input logic [NR_PORTS-1:0][63:0] data_wdata_i,
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input logic [NR_PORTS-1:0] data_req_i,
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input logic [NR_PORTS-1:0] data_we_i,
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input logic [NR_PORTS-1:0][7:0] data_be_i,
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input logic [NR_PORTS-1:0] kill_req_i,
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input logic [NR_PORTS-1:0] tag_valid_i,
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output logic [NR_PORTS-1:0] data_gnt_o,
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output logic [NR_PORTS-1:0] data_rvalid_o,
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output logic [NR_PORTS-1:0][63:0] data_rdata_o
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);
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// one-hot encoded
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localparam DATA_WIDTH = NR_PORTS;
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// remember the request port in case of a multi-cycle transaction
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logic [DATA_WIDTH-1:0] request_port_n, request_port_q;
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// local ports
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// FIFO control ports
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logic full;
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logic empty;
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logic single_element;
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// FIFO input port
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logic [DATA_WIDTH-1:0] in_data;
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logic push;
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// FIFO output port
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logic [DATA_WIDTH-1:0] out_data;
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logic pop;
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// FIFO to keep track of the responses
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fifo #(
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.dtype ( logic [DATA_WIDTH-1:0] ),
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.DEPTH ( 4 )
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) fifo_i (
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.single_element_o ( single_element ),
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// the flush is accomplished implicitly by waiting for the queue to be drained before accepting any new request
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// it is the responsibility of the attached units to make sure it handles any outstanding responses
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.flush_i ( 1'b0 ),
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.full_o ( full ),
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.empty_o ( empty ),
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.data_i ( in_data ),
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.push_i ( push ),
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.data_o ( out_data ),
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.pop_i ( pop )
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);
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// addressing read and full write
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always_comb begin : read_req_write
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automatic logic [DATA_WIDTH-1:0] request_index = request_port_q;
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data_req_o = 1'b0;
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in_data = '{default: 0};
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push = 1'b0;
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request_port_n = request_port_q;
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for (int i = 0; i < NR_PORTS; i++)
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data_gnt_o[i] = 1'b0;
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// ----------------------------
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// Single-cycle memory requests
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// ----------------------------
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// only go for a new request if we can wait for the valid e.g.: we have enough space in the buffer
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if (~full) begin
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for (int unsigned i = 0; i < NR_PORTS; i++) begin
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if (data_req_i[i] == 1'b1) begin
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data_req_o = data_req_i[i];
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// save the request port for future states
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request_port_n = i;
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request_index = i;
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// wait for the grant
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// set the slave on which we are waiting
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in_data = 1'b1 << i[DATA_WIDTH-1:0];
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break; // break here as this is a priority select
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end
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end
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// only if we got a grant save it to the queue
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if (data_gnt_i) begin
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push = 1'b1;
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end
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end
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// pass through all signals from the correct slave port
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address_index_o = address_index_i[request_index];
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data_wdata_o = data_wdata_i[request_index];
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data_be_o = data_be_i[request_index];
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data_we_o = data_we_i[request_index];
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data_gnt_o[request_index] = data_gnt_i;
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// the following signals are to be passed through one-cycle later
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address_tag_o = address_tag_i[request_port_q];
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kill_req_o = kill_req_i[request_port_q];
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tag_valid_o = tag_valid_i[request_port_q];
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end
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// ------------
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// Read port
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// ------------
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// results, listening on the input signals of the slave port
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genvar i;
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// this is very timing sensitive since we can give a new request if we got an rvalid
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// hence this combines the to most critical paths (from and to memory)
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generate
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// default assignment & one hot decoder
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for (i = 0; i < NR_PORTS; i++) begin
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assign data_rvalid_o[i] = out_data[i] & data_rvalid_i;
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assign data_rdata_o[i] = data_rdata_i;
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end
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endgenerate
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always_comb begin : slave_read_port
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pop = 1'b0;
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// if there is a valid signal the FIFO should not be empty anyway
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if (data_rvalid_i) begin
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pop = 1'b1;
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end
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end
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// sequential process
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (~rst_ni) begin
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request_port_q <= 'b0;
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end else begin
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request_port_q <= request_port_n;
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end
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end
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// ------------
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// Assertions
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// ------------
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`ifndef SYNTHESIS
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`ifndef VERILATOR
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// make sure that we eventually get an rvalid after we received a grant
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assert property (@(posedge clk_i) data_gnt_i |-> ##[1:$] data_rvalid_i )
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else begin $error("There was a grant without a rvalid"); $stop(); end
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// assert that there is no grant without a request
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assert property (@(negedge clk_i) data_gnt_i |-> data_req_o)
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else begin $error("There was a grant without a request."); $stop(); end
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// assert that the address does not contain X when request is sent
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assert property ( @(posedge clk_i) (data_req_o) |-> (!$isunknown(address_index_o)) )
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else begin $error("address contains X when request is set"); $stop(); end
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// there should be no rvalid when we are in IDLE
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// assert property (
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// @(posedge clk) (CS == IDLE) |-> (data_rvalid_i == 1'b0) )
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// else begin $error("Received rvalid while in IDLE state"); $stop(); end
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// assert that errors are only sent at the same time as grant or rvalid
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// assert property ( @(posedge clk) (data_err_i) |-> (data_gnt_i || data_rvalid_i) )
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// else begin $error("Error without data grant or rvalid"); $stop(); end
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`endif
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`endif
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endmodule
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@ -102,7 +102,8 @@ module ex_stage #(
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input logic instr_if_data_rvalid_i,
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input logic [63:0] instr_if_data_rdata_i,
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AXI_BUS.Master data_if
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AXI_BUS.Master data_if,
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AXI_BUS.Master bypass_if
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);
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// -----
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11
src/lsu.sv
11
src/lsu.sv
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@ -65,6 +65,7 @@ module lsu #(
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input logic [63:0] instr_if_data_rdata_i,
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// Data cache refill port
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AXI_BUS.Master data_if,
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AXI_BUS.Master bypass_if,
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output exception_t lsu_exception_o // to WB, signal exception status LD/ST exception
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@ -143,6 +144,7 @@ module lsu #(
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nbdcache i_nbdcache (
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// to D$
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.data_if ( data_if ),
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.bypass_if ( bypass_if ),
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// from PTW, Load Unit and Store Unit
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.address_index_i ( address_index_i ),
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.address_tag_i ( address_tag_i ),
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@ -156,9 +158,12 @@ module lsu #(
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.data_rvalid_o ( data_rvalid_o ),
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.data_rdata_o ( data_rdata_o ),
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.amo_op_i ( amo_op_i ),
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.amo_commit_i (),
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.amo_valid_o (),
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.amo_result_o (),
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.amo_commit_i ( ),
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.amo_valid_o ( ),
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.amo_result_o ( ),
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.amo_flush_i ( 1'b0 ),
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.enable_i ( 1'b0 ),
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.*
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);
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115
src/miss_arbiter.sv
Normal file
115
src/miss_arbiter.sv
Normal file
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@ -0,0 +1,115 @@
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// Author: Florian Zaruba, ETH Zurich
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// Date: 24.4.2017
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// Description: Arbitrates the dcache ports
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//
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//
|
||||
// Copyright (C) 2017 ETH Zurich, University of Bologna
|
||||
// All rights reserved.
|
||||
//
|
||||
// This code is under development and not yet released to the public.
|
||||
// Until it is released, the code is under the copyright of ETH Zurich and
|
||||
// the University of Bologna, and may contain confidential and/or unpublished
|
||||
// work. Any reuse/redistribution is strictly forbidden without written
|
||||
// permission from ETH Zurich.
|
||||
//
|
||||
// Bug fixes and contributions will eventually be released under the
|
||||
// SolderPad open hardware license in the context of the PULP platform
|
||||
// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the
|
||||
// University of Bologna.
|
||||
//
|
||||
import ariane_pkg::*;
|
||||
|
||||
module miss_arbiter #(
|
||||
parameter int unsigned NR_PORTS = 3
|
||||
)(
|
||||
input logic clk_i, // Clock
|
||||
input logic rst_ni, // Asynchronous reset active low
|
||||
// master ports
|
||||
input logic [NR_PORTS-1:0] data_req_i,
|
||||
input logic [NR_PORTS-1:0][63:0] address_i,
|
||||
input logic [NR_PORTS-1:0][63:0] data_wdata_i,
|
||||
input logic [NR_PORTS-1:0] data_we_i,
|
||||
input logic [NR_PORTS-1:0][7:0] data_be_i,
|
||||
output logic [NR_PORTS-1:0] data_gnt_o,
|
||||
output logic [NR_PORTS-1:0] data_rvalid_o,
|
||||
output logic [NR_PORTS-1:0][63:0] data_rdata_o,
|
||||
// slave port
|
||||
input logic [$clog2(NR_PORTS)-1:0] id_i,
|
||||
output logic [$clog2(NR_PORTS)-1:0] id_o,
|
||||
output logic data_req_o,
|
||||
output logic [63:0] address_o,
|
||||
output logic [63:0] data_wdata_o,
|
||||
output logic data_we_o,
|
||||
output logic [7:0] data_be_o,
|
||||
input logic data_gnt_i,
|
||||
input logic data_rvalid_i,
|
||||
input logic [63:0] data_rdata_i
|
||||
);
|
||||
|
||||
|
||||
// addressing read and full write
|
||||
always_comb begin : read_req_write
|
||||
automatic logic [$clog2(NR_PORTS)-1:0] request_index = 0;
|
||||
|
||||
data_req_o = 1'b0;
|
||||
data_gnt_o = '0;
|
||||
|
||||
for (int unsigned i = 0; i < NR_PORTS; i++) begin
|
||||
if (data_req_i[i] == 1'b1) begin
|
||||
data_req_o = data_req_i[i];
|
||||
request_index = i;
|
||||
break; // break here as this is a priority select
|
||||
end
|
||||
end
|
||||
|
||||
// pass through all signals from the correct slave port
|
||||
address_o = address_i[request_index];
|
||||
data_wdata_o = data_wdata_i[request_index];
|
||||
data_be_o = data_be_i[request_index];
|
||||
data_we_o = data_we_i[request_index];
|
||||
data_gnt_o[request_index] = data_gnt_i;
|
||||
id_o = request_index;
|
||||
end
|
||||
|
||||
// ------------
|
||||
// Read port
|
||||
// ------------
|
||||
|
||||
always_comb begin : slave_read_port
|
||||
data_rvalid_o = '0;
|
||||
data_rdata_o = '0;
|
||||
// if there is a valid signal the FIFO should not be empty anyway
|
||||
if (data_rvalid_i) begin
|
||||
data_rvalid_o[id_i] = data_rvalid_i;
|
||||
data_rdata_o [id_i] = data_rdata_i;
|
||||
end
|
||||
end
|
||||
|
||||
// ------------
|
||||
// Assertions
|
||||
// ------------
|
||||
|
||||
`ifndef SYNTHESIS
|
||||
`ifndef VERILATOR
|
||||
// make sure that we eventually get an rvalid after we received a grant
|
||||
assert property (@(posedge clk_i) data_gnt_i |-> ##[1:$] data_rvalid_i )
|
||||
else begin $error("There was a grant without a rvalid"); $stop(); end
|
||||
// assert that there is no grant without a request
|
||||
assert property (@(negedge clk_i) data_gnt_i |-> data_req_o)
|
||||
else begin $error("There was a grant without a request."); $stop(); end
|
||||
// assert that the address does not contain X when request is sent
|
||||
assert property ( @(posedge clk_i) (data_req_o) |-> (!$isunknown(address_o)) )
|
||||
else begin $error("address contains X when request is set"); $stop(); end
|
||||
|
||||
// there should be no rvalid when we are in IDLE
|
||||
// assert property (
|
||||
// @(posedge clk) (CS == IDLE) |-> (data_rvalid_i == 1'b0) )
|
||||
// else begin $error("Received rvalid while in IDLE state"); $stop(); end
|
||||
|
||||
// assert that errors are only sent at the same time as grant or rvalid
|
||||
// assert property ( @(posedge clk) (data_err_i) |-> (data_gnt_i || data_rvalid_i) )
|
||||
// else begin $error("Error without data grant or rvalid"); $stop(); end
|
||||
|
||||
`endif
|
||||
`endif
|
||||
endmodule
|
||||
84
src/miss_handler.sv
Executable file
84
src/miss_handler.sv
Executable file
|
|
@ -0,0 +1,84 @@
|
|||
// --------------
|
||||
// MISS Handler
|
||||
// --------------
|
||||
//
|
||||
// Description: Handles cache misses.
|
||||
//
|
||||
import nbdcache_pkg::*;
|
||||
|
||||
module miss_handler #(
|
||||
parameter int unsigned NR_PORTS = 3
|
||||
)(
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
input logic [NR_PORTS-1:0][$bits(miss_req_t)-1:0] miss_req_i,
|
||||
output logic [NR_PORTS-1:0] miss_gnt_o,
|
||||
output logic [NR_PORTS-1:0] miss_valid_o,
|
||||
output logic [NR_PORTS-1:0][63:0] miss_data_o,
|
||||
AXI_BUS.Master bypass_if
|
||||
// update cache
|
||||
);
|
||||
|
||||
// ------------------
|
||||
// Cacheline Refills
|
||||
// ------------------
|
||||
|
||||
// ------------------
|
||||
// Bypass
|
||||
// ------------------
|
||||
// AXI Adapter
|
||||
// request from FSM
|
||||
|
||||
// Hack as system verilog support in modelsim seems to be buggy here
|
||||
miss_req_t miss_req;
|
||||
assign miss_req = miss_req_t'(miss_req_i);
|
||||
|
||||
miss_req_t req_fsm_bypass;
|
||||
logic gnt_bypass_fsm;
|
||||
logic valid_bypass_fsm;
|
||||
logic [63:0] data_bypass_fsm;
|
||||
logic [$clog2(NR_PORTS)-1:0] id_bypass_fsm, id_fsm_bypass;
|
||||
|
||||
miss_arbiter i_bypass_arbiter (
|
||||
// Master Side
|
||||
.data_req_i ( miss_req.valid & miss_req.bypass ),
|
||||
.address_i ( miss_req.addr ),
|
||||
.data_wdata_i ( miss_req.wdata ),
|
||||
.data_we_i ( miss_req.we ),
|
||||
.data_be_i ( miss_req.be ),
|
||||
.data_gnt_o ( miss_gnt_o ),
|
||||
.data_rvalid_o ( miss_valid_o ),
|
||||
.data_rdata_o ( miss_data_o ),
|
||||
// Slave Side
|
||||
.id_i ( id_bypass_fsm ),
|
||||
.id_o ( id_fsm_bypass ),
|
||||
.address_o ( req_fsm_bypass.addr ),
|
||||
.data_wdata_o ( req_fsm_bypass.wdata ),
|
||||
.data_req_o ( req_fsm_bypass.valid ),
|
||||
.data_we_o ( req_fsm_bypass.we ),
|
||||
.data_be_o ( req_fsm_bypass.be ),
|
||||
.data_gnt_i ( gnt_bypass_fsm ),
|
||||
.data_rvalid_i ( valid_bypass_fsm ),
|
||||
.data_rdata_i ( data_bypass_fsm ),
|
||||
.*
|
||||
);
|
||||
|
||||
axi_adapter i_bypass_axi_adapter (
|
||||
.req_i ( miss_req.valid ),
|
||||
.type_i ( SINGLE_REQ ),
|
||||
.gnt_o ( gnt_bypass_fsm ),
|
||||
.addr_i ( req_fsm_bypass.addr ),
|
||||
.we_i ( req_fsm_bypass.we ),
|
||||
.wdata_i ( req_fsm_bypass.wdata ),
|
||||
.be_i ( req_fsm_bypass.be ),
|
||||
.id_i ( id_fsm_bypass ),
|
||||
.valid_o ( miss_valid_o ),
|
||||
.rdata_o ( miss_data_o ),
|
||||
.id_o ( id_bypass_fsm ),
|
||||
.critical_word_o ( ), // not used for single requests
|
||||
.critical_word_valid ( ), // not used for single requests
|
||||
.axi ( bypass_if ),
|
||||
.*
|
||||
);
|
||||
|
||||
endmodule
|
||||
108
src/nbdcache.sv
108
src/nbdcache.sv
|
|
@ -19,7 +19,7 @@
|
|||
import ariane_pkg::*;
|
||||
import nbdcache_pkg::*;
|
||||
|
||||
module nb_dcache #(
|
||||
module nbdcache #(
|
||||
parameter int unsigned INDEX_WIDTH = 12,
|
||||
parameter int unsigned TAG_WIDTH = 44,
|
||||
parameter int unsigned CACHE_LINE_WIDTH = 256,
|
||||
|
|
@ -27,10 +27,13 @@ module nb_dcache #(
|
|||
parameter int unsigned AXI_ID_WIDTH = 10,
|
||||
parameter int unsigned AXI_USER_WIDTH = 10
|
||||
)(
|
||||
input logic clk_i, // Clock
|
||||
input logic rst_ni, // Asynchronous reset active low
|
||||
// AXI refill port
|
||||
input logic clk_i, // Clock
|
||||
input logic rst_ni, // Asynchronous reset active low
|
||||
// Cache control
|
||||
input logic enable_i, // from CSR
|
||||
// Cache AXI refill port
|
||||
AXI_BUS.Master data_if,
|
||||
AXI_BUS.Master bypass_if,
|
||||
// AMO interface
|
||||
input logic amo_commit_i, // commit atomic memory operation
|
||||
output logic amo_valid_o, // we have a valid AMO result
|
||||
|
|
@ -54,14 +57,72 @@ module nb_dcache #(
|
|||
localparam NUM_WORDS = 2**INDEX_WIDTH;
|
||||
localparam DIRTY_WIDTH = (CACHE_LINE_WIDTH/64)*SET_ASSOCIATIVITY;
|
||||
|
||||
// AMO ALU
|
||||
logic [2:0][$bits(miss_req_t)-1:0] miss_req;
|
||||
logic [2:0] miss_gnt;
|
||||
logic [2:0] miss_valid;
|
||||
logic [2:0][63:0] miss_data;
|
||||
|
||||
logic [SET_ASSOCIATIVITY-1:0] req;
|
||||
logic [SET_ASSOCIATIVITY-1:0][INDEX_WIDTH-1:0] adrr;
|
||||
logic [SET_ASSOCIATIVITY-1:0][CACHE_LINE_WIDTH-1:0] tag;
|
||||
logic [SET_ASSOCIATIVITY-1:0][TAG_WIDTH-1:0] data;
|
||||
logic [SET_ASSOCIATIVITY-1:0] we;
|
||||
|
||||
// Cache FSM
|
||||
// ------------------
|
||||
// Cache Controller
|
||||
// ------------------
|
||||
generate
|
||||
for (genvar i = 0; i < 3; i++) begin : master_ports
|
||||
cache_ctrl #(
|
||||
.SET_ASSOCIATIVITY ( SET_ASSOCIATIVITY ),
|
||||
.INDEX_WIDTH ( INDEX_WIDTH ),
|
||||
.TAG_WIDTH ( TAG_WIDTH ),
|
||||
.CACHE_LINE_WIDTH ( CACHE_LINE_WIDTH )
|
||||
) i_cache_ctrl (
|
||||
.bypass_i ( ~enable_i ),
|
||||
.address_index_i ( address_index_i [i] ),
|
||||
.address_tag_i ( address_tag_i [i] ),
|
||||
.data_wdata_i ( data_wdata_i [i] ),
|
||||
.data_req_i ( data_req_i [i] ),
|
||||
.data_we_i ( data_we_i [i] ),
|
||||
.data_be_i ( data_be_i [i] ),
|
||||
.kill_req_i ( kill_req_i [i] ),
|
||||
.tag_valid_i ( tag_valid_i [i] ),
|
||||
.data_gnt_o ( data_gnt_o [i] ),
|
||||
.data_rvalid_o ( data_rvalid_o [i] ),
|
||||
.data_rdata_o ( data_rdata_o [i] ),
|
||||
.amo_op_i ( amo_op_i [i] ),
|
||||
|
||||
.req_o ( req ),
|
||||
.adrr_o ( adrr ),
|
||||
.tag_i ( tag ),
|
||||
.data_i ( data ),
|
||||
.we_o ( we ),
|
||||
|
||||
.miss_req_o ( miss_req [i] ),
|
||||
.miss_gnt_i ( miss_gnt [i] ),
|
||||
.miss_valid_i ( miss_valid [i] ),
|
||||
.miss_data_i ( miss_data [i] ),
|
||||
.mshr_addr_o ( ), // TODO
|
||||
.mashr_addr_matches_i ( ), // TODO
|
||||
.*
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// ------------------
|
||||
// Miss Handling Unit
|
||||
// ------------------
|
||||
miss_handler i_miss_handler (
|
||||
.miss_req_i ( miss_req ),
|
||||
.miss_gnt_o ( miss_gnt ),
|
||||
.miss_valid_o ( miss_valid ),
|
||||
.miss_data_o ( miss_data ),
|
||||
.*
|
||||
);
|
||||
|
||||
// --------------
|
||||
// Memories
|
||||
// Memory Arrays
|
||||
// --------------
|
||||
// TODO: Re-work
|
||||
generate
|
||||
|
|
@ -108,8 +169,6 @@ module nb_dcache #(
|
|||
.rdata_o ( )
|
||||
);
|
||||
|
||||
// AXI Module
|
||||
|
||||
`ifndef SYNTHESIS
|
||||
initial begin
|
||||
assert ($bits(data_if.aw_addr) == 64) else $fatal(1, "Ariane needs a 64-bit bus");
|
||||
|
|
@ -117,3 +176,34 @@ module nb_dcache #(
|
|||
end
|
||||
`endif
|
||||
endmodule
|
||||
|
||||
// --------------
|
||||
// Memory Arbiter
|
||||
// --------------
|
||||
//
|
||||
// Description: Arbitrates access to cache memories
|
||||
//
|
||||
module sram_arbiter #(
|
||||
parameter int unsigned NR_PORTS = 3
|
||||
)(
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
input logic [NR_PORTS-1:0] req_i,
|
||||
output logic [NR_PORTS-1:0] gnt_o
|
||||
);
|
||||
|
||||
always_comb begin
|
||||
|
||||
gnt_o = '0;
|
||||
|
||||
// priority select
|
||||
for (int i = 0; i < NR_PORTS; i++) begin
|
||||
if (req_i[i]) begin
|
||||
gnt_o[i] = 1'b1;
|
||||
break;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue