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https://github.com/openhwgroup/cva6.git
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improve dashboard-provided log (#2636)
* Due to the increased count of warnings, provide tail of log instead of head on the dashboard * Add tandem yaml report file on the jobs reports * Reduce UVM Verbosity on smoke gen tests
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7c326f5407
commit
160c322f53
4 changed files with 17 additions and 8 deletions
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@ -131,8 +131,8 @@ build_tools:
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- echo $SYN_VCS_BASHRC; source $SYN_VCS_BASHRC
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.simu_after_script: &simu_after_script
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- for i in $(find verif/sim/out*/[vq]*_sim -type f \( -name "*.csv" -o -name "*.iss" -o -name "*.yaml" \)) ; do head -10000 $i > artifacts/logs/$(basename $i).head ; done
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- head -10000 verif/sim/logfile.log > artifacts/logs/logfile.log.head
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- for i in $(find verif/sim/out*/[vq]*_sim -type f \( -name "*.csv" -o -name "*.iss" -o -name "*.yaml" \)) ; do tail -10000 $i > artifacts/logs/$(basename $i) ; done
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- tail -10000 verif/sim/logfile.log > artifacts/logs/logfile.log
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- if [ -n "$SPIKE_TANDEM" ]; then python3 .gitlab-ci/scripts/report_tandem.py verif/sim/out*/"$DV_SIMULATORS"_sim; else python3 .gitlab-ci/scripts/report_simu.py verif/sim/logfile.log; fi
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smoke-tests:
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@ -45,9 +45,9 @@ for i in list_of_tests:
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if with_logs:
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logsPath = "logs/" + os.environ.get("CI_JOB_ID") + "/artifacts/logs/"
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output_log = logsPath + 'logfile.log.head'
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tb_log = logsPath + test + "." + target + '.log.iss.head'
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disassembly = logsPath + test + "." + target + '.csv.head'
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output_log = logsPath + 'logfile.log'
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tb_log = logsPath + test + "." + target + '.log.iss'
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disassembly = logsPath + test + "." + target + '.csv'
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col = [target, isa, test, output_log, tb_log, disassembly]
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else:
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col = [target, isa, test]
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@ -47,6 +47,7 @@ def add_table_legend(metrics_table, with_logs):
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if with_logs:
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metrics_table.add_column("OUTPUT", "log")
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metrics_table.add_column("TANDEM REPORT", "log")
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metrics_table.add_column("TB LOGS", "log")
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metrics_table.add_column("DISASSEMBLY", "log")
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@ -74,13 +75,15 @@ def add_test_row(report_file, metrics_table, with_logs):
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if with_logs:
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logs_path = "logs/" + os.environ.get("CI_JOB_ID") + "/artifacts/logs/"
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output_log = logs_path + "logfile.log.head"
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output_log = logs_path + "logfile.log"
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log_prefix = logs_path + report['test'] + "_" + str(report["iteration"]) + "." + report["target"] \
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if "iteration" in report else logs_path + report['test'] + "." + report["target"]
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tb_log = log_prefix + '.log.iss.head'
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disassembly = log_prefix + '.log.csv.head'
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tb_log = log_prefix + '.log.iss'
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disassembly = log_prefix + '.log.csv'
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tandem_report = log_prefix + '.log.yaml'
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row.append(output_log)
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row.append(tandem_report)
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row.append(tb_log)
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row.append(disassembly)
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@ -33,6 +33,12 @@ if ! [ -n "$DV_TARGET" ]; then
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DV_TARGET=cv32a65x
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fi
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if ! [ -n "$UVM_VERBOSITY" ]; then
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export UVM_VERBOSITY=UVM_NONE
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fi
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export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
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cd verif/sim/
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cp ../env/corev-dv/custom/riscv_custom_instr_enum.sv ./dv/src/isa/custom/
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python3 cva6.py --testlist=cva6_base_testlist.yaml --test riscv_arithmetic_basic_test_comp --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imcb/ --mabi ilp32 --isa rv32imc --isa_extension="zba,zbb,zbc,zbs,zcb" --simulator_yaml ../env/corev-dv/simulator.yaml --iss=$DV_SIMULATORS $DV_OPTS --priv=m -i 1 --iss_timeout 300
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