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Fix gate simulation: Update hpdcache_sram black box (#2632)
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Update hpdcache_sram black box which changed with bump of hpdcache repository
This commit is contained in:
Guillaume Chauvon 2024-11-27 14:45:15 +01:00 • committed by GitHub
parent 6ee7a7d0c2
commit 7c326f5407
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GPG key ID: B5690EEEBB952194
4 changed files with 8 additions and 7 deletions
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5
.gitlab-ci.yml
View file

@ -275,6 +275,7 @@ asic-synthesis:
- echo $DV_TARGET
- source ./verif/sim/setup-env.sh
- git clone ${SYNTH_SCRIPT} ${SYNTH_SCRIPT_PATH} -b ${SYNTH_SCRIPT_BRANCH}
- git -C ${SYNTH_SCRIPT_PATH} checkout 1e166766d2c91ca905577cccc70813a2a8bbefc2
- cp -r ${SYNTH_SCRIPT_PATH}/cva6/ ../
- git apply ${SYNTH_SCRIPT_PATH}/patches/*.patch
- echo $SYN_DCSHELL_BASHRC; source $SYN_DCSHELL_BASHRC
@ -544,8 +545,8 @@ simu-gate:
- !reference [.copy_spike_artifacts]
- echo $PERIOD
- source ./verif/sim/setup-env.sh
- git clone ${SYNTH_SCRIPT} ${SYNTH_SCRIPT_PATH} -b testelf
- git -C ${SYNTH_SCRIPT_PATH} checkout cb92f846
- git clone ${SYNTH_SCRIPT} ${SYNTH_SCRIPT_PATH} -b ${SYNTH_SCRIPT_BRANCH}
- git -C ${SYNTH_SCRIPT_PATH} checkout 1e166766d2c91ca905577cccc70813a2a8bbefc2
- cp -r ${SYNTH_SCRIPT_PATH}/cva6/ ../
- git apply ${SYNTH_SCRIPT_PATH}/patches/*.patch
- source verif/regress/install-riscv-tests.sh

2
core/Flist.cva6_gate
View file

@ -62,7 +62,7 @@ ${CVA6_REPO_DIR}/pd/synth/cva6_${TARGET_CFG}_synth.v
# Dedicated to black box in caches, cv32a65x only
${CVA6_REPO_DIR}/pd/synth/tc_sram_wrapper_256_64_00000008_00000001_00000001_none_0.sv
${CVA6_REPO_DIR}/pd/synth/hpdcache_sram_wbyteenable_1rw_00000007_00000040_00000080.sv
${CVA6_REPO_DIR}/pd/synth/hpdcache_sram_1rw_00000006_0000001a_00000040.sv
${CVA6_REPO_DIR}/pd/synth/hpdcache_sram_1rw_00000006_0000001c_00000040.sv
${CVA6_REPO_DIR}/common/local/util/tc_sram_wrapper.sv
${CVA6_REPO_DIR}/common/local/util/tc_sram_wrapper_cache_techno.sv

2
pd/synth/Makefile
View file

@ -60,7 +60,7 @@ rm_synth: pre_cva6_synth
cp Flist.cva6_synth ../../$(SYNTH_FLOW_NAME)/synth/
CVA6_REPO_DIR=$(CVA6_REPO_DIR) make -C ../../$(SYNTH_FLOW_NAME)/synth/ platform_synth_topo
sed -i -n -e '/module hpdcache_sram_wbyteenable_1rw_00000007_00000040_00000080/,/endmodule/!p' $(DESIGN_NAME)_$(TARGET)_synth.v
sed -i -n -e '/module hpdcache_sram_1rw_00000006_0000001a_00000040/,/endmodule/!p' $(DESIGN_NAME)_$(TARGET)_synth.v
sed -i -n -e '/module hpdcache_sram_1rw_00000006_0000001c_00000040/,/endmodule/!p' $(DESIGN_NAME)_$(TARGET)_synth.v
echo $(NAND2_AREA) > $(DESIGN_NAME)_$(TARGET)/nand2area.txt
cva6_read:

6
pd/synth/hpdcache_sram_1rw_00000006_0000001a_00000040.sv → pd/synth/hpdcache_sram_1rw_00000006_0000001c_00000040.sv
View file

@ -23,10 +23,10 @@
* Description : SRAM behavioral model
* History :
*/
module hpdcache_sram_1rw_00000006_0000001a_00000040
module hpdcache_sram_1rw_00000006_0000001c_00000040
#(
parameter int unsigned ADDR_SIZE = 6,
parameter int unsigned DATA_SIZE = 26,
parameter int unsigned DATA_SIZE = 28,
parameter int unsigned DEPTH = 2**ADDR_SIZE
)
(
@ -57,4 +57,4 @@ module hpdcache_sram_1rw_00000006_0000001a_00000040
rdata <= mem[addr];
end
end : mem_update_ff
endmodule : hpdcache_sram_1rw_00000006_0000001a_00000040
endmodule : hpdcache_sram_1rw_00000006_0000001c_00000040