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fpga: Fix empty match file in flow (#334)

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Jimmy Situ 2019-10-08 16:48:29 +08:00 • committed by Florian Zaruba
parent f66b2f1937
commit 17f430429f
1 changed files with 1 additions and 1 deletions
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2
fpga/scripts/run.tcl
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@ -39,7 +39,7 @@ if {$::env(BOARD) eq "genesys2"} {
exit 1
}
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file" "*$registers"]]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file" "*/$registers"]]
set_property -dict { file_type {Verilog Header} is_global_include 1} -objects $file_obj
update_compile_order -fileset sources_1