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🚧 Instantiate Hart Ctrl

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This commit is contained in:
Florian Zaruba 2018-07-10 11:35:12 -07:00
parent eb95474ace
commit 1f7244e1a0
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5 changed files with 125 additions and 64 deletions
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9
Makefile
View file

@ -178,8 +178,13 @@ verilate:
$(filter-out src/debug/dm_pkg.sv, $(wildcard src/debug/*.sv)) src/util/generic_fifo.sv tb/common/SimDTM.v \
src/util/cluster_clock_gating.sv src/util/behav_sram.sv src/axi_mem_if/src/axi2mem.sv tb/agents/axi_if/axi_if.sv \
+incdir+src/axi_node --vpi --trace-structs \
--unroll-count 256 -Wno-fatal -Werror-PINMISSING -Werror-IMPLICIT -LDFLAGS "-lfesvr" -CFLAGS "-std=c++11" -Wall --cc --trace \
-Wno-PINCONNECTEMPTY -Wno-DECLFILENAME -Wno-UNOPTFLAT -Wno-UNUSED \
--unroll-count 256 -Werror-PINMISSING -Werror-IMPLICIT -LDFLAGS "-lfesvr" -CFLAGS "-std=c++11" -Wall --cc --trace \
-Wno-fatal \
-Wno-PINCONNECTEMPTY \
-Wno-DECLFILENAME \
-Wno-UNOPTFLAT \
-Wno-UNUSED \
-Wno-ASSIGNDLY \
$(list_incdir) --top-module ariane_wrapped --exe tb/ariane_tb.cpp tb/dpi/SimDTM.cc
cd obj_dir && make -j8 -f Variane_wrapped.mk

25
src/ariane_wrapped.sv
View file

@ -31,6 +31,7 @@ module ariane_wrapped #(
// disable test-enable
logic test_en;
logic ndmreset;
logic ndmreset_n;
logic debug_req;
logic debug_req_valid;
@ -44,6 +45,7 @@ module ariane_wrapped #(
logic [31:0] debug_resp_bits_data;
assign test_en = 1'b0;
assign ndmreset_n = ~ndmreset;
localparam NB_SLAVE = 3;
localparam NB_MASTER = 2;
@ -89,6 +91,7 @@ module ariane_wrapped #(
.clk_i ( clk_i ),
.rst_ni ( rst_ni ), // PoR
.ndmreset_o ( ndmreset ),
.dmactive_o ( ), // active debug session
.debug_req_o ( debug_req ),
.axi_slave ( master[0] ),
.dmi_rst_ni ( rst_ni ),
@ -125,15 +128,15 @@ module ariane_wrapped #(
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI_USER_WIDTH ( AXI_USER_WIDTH )
) i_axi2mem (
.clk_i ( clk_i ),
.rst_ni ( ndmreset ),
.slave ( master[1] ),
.req_o ( req ),
.we_o ( we ),
.addr_o ( addr ),
.be_o ( be ),
.data_o ( wdata ),
.data_i ( rdata )
.clk_i ( clk_i ),
.rst_ni ( ndmreset_n ),
.slave ( master[1] ),
.req_o ( req ),
.we_o ( we ),
.addr_o ( addr ),
.be_o ( be ),
.data_o ( wdata ),
.data_i ( rdata )
);
sram #(
@ -162,7 +165,7 @@ module ariane_wrapped #(
.AXI_ID_WIDTH ( AXI_ID_WIDTH )
) i_axi_xbar (
.clk ( clk_i ),
.rst_n ( ndmreset ),
.rst_n ( ndmreset_n ),
.test_en_i ( test_en ),
.slave ( slave ),
.master ( master ),
@ -179,7 +182,7 @@ module ariane_wrapped #(
.AXI_USER_WIDTH ( AXI_USER_WIDTH )
) i_ariane (
.clk_i ( clk_i ),
.rst_ni ( ndmreset ),
.rst_ni ( ndmreset_n ),
.test_en_i ( test_en ),
.boot_addr_i ( CACHE_START_ADDR ),
.core_id_i ( '0 ),

3
src/debug/dm_csrs.sv
View file

@ -213,7 +213,7 @@ module dm_csrs #(
dmcontrol_d.clrresethaltreq = 1'b0;
dmcontrol_d.zero1 = '0;
dmcontrol_d.zero0 = '0;
// TODO(zarubaf)
// Non-writeable, clear only
dmcontrol_d.ackhavereset = 1'b0;
end
@ -266,6 +266,7 @@ module dm_csrs #(
dmcontrol_q.setresethaltreq <= '0;
dmcontrol_q.clrresethaltreq <= '0;
dmcontrol_q.ndmreset <= '0;
// this is the only write-able bit during reset
dmcontrol_q.dmactive <= dmcontrol_d.dmactive;
cmderr_q <= dm::CmdErrNone;
command_q <= '0;

59
src/debug/dm_ctrl.sv
View file

@ -16,15 +16,13 @@
*
*/
module dm_ctrl #(
parameter dm::hartinfo_t HartInfo = '0
)(
module dm_ctrl (
input logic clk_i, // Clock
input logic dmactive_i, // synchronous low active reset
input logic dmactive_i, // synchronous low active reset, same as hart
input logic ndmreset_i, // non-debug module reset
output logic debug_req_o,
// to/from CSRs
// status
output logic hartinfo_o,
output logic halted_o,
output logic running_o,
output logic unavailable_o,
@ -38,43 +36,72 @@ module dm_ctrl #(
input dm::command_t command_i,
output logic set_cmderror_o,
output dm::cmderr_t cmderror_o,
output logic cmdbusy_o
output logic cmdbusy_o,
// from AXI module
input logic ackhalt_i // hart acknowledged halt request
);
assign hartinfo_o = HartInfo;
logic havereset_d, havereset_q;
// assignments
assign havereset_o = havereset_q;
typedef enum logic [1:0] {
kReset, kRunning
kRunning, kHaltReq, kHalted
} state_t;
state_t state_d, state_q;
always_comb begin
state_d = state_q;
state_d = state_q;
halted_o = 1'b0;
running_o = 1'b0;
unavailable_o = 1'b0;
havereset_o = 1'b0;
resumeack_o = 1'b0;
debug_req_o = 1'b0;
unique case (state_q)
kReset: begin
havereset_o = 1'b1;
if (ackhavereset_i) state_d = kRunning;
end
kRunning: begin
if (haltreq_i) state_d = kHaltReq;
end
kHaltReq: begin
// request entering debug mode
debug_req_o = 1'b1;
// hart acknowledged ~> halt
if (ackhalt_i) state_d = kHalted;
end
kHalted: begin
end
endcase
end
always_comb begin : hart_reset_ctrl
havereset_d = havereset_q;
// clear havereset_d flag
if (ackhavereset_i) begin
havereset_d = 1'b0;
end
// go in reset mode again
if (ndmreset_i) begin
havereset_d = 1'b1;
end
end
// sequential process
always_ff @(posedge clk_i) begin
if (~dmactive_i) begin
state_q <= kIdle;
state_q <= kRunning;
havereset_q <= 1'b1;
end else begin
state_q <= state_d;
state_q <= state_d;
havereset_q <= havereset_d;
end
end
endmodule

93
src/debug/dm_top.sv
View file

@ -23,6 +23,7 @@ module dm_top #(
input logic clk_i, // clock
input logic rst_ni, // asynchronous reset active low, connect PoR here, not the system reset
output logic ndmreset_o, // non-debug module reset
output logic dmactive_o, // debug module is active
output logic [NrHarts-1:0] debug_req_o, // async debug request
AXI_BUS.Slave axi_slave, // bus slave
// Connection to DTM - compatible to RocketChip Debug Module
@ -40,24 +41,21 @@ module dm_top #(
);
// Debug CSRs
logic dmactive_o;
dm::hartinfo_t [NrHarts-1:0] hartinfo_i;
logic [NrHarts-1:0] halted_i;
logic [NrHarts-1:0] running_i;
logic [NrHarts-1:0] unavailable_i;
logic [NrHarts-1:0] havereset_i;
logic [NrHarts-1:0] resumeack_i;
logic [NrHarts-1:0] haltreq_o;
logic [NrHarts-1:0] resumereq_o;
logic [NrHarts-1:0] ackhavereset_o;
logic command_write_o;
dm::command_t command_o;
logic [NrHarts-1:0] set_cmderror_i;
dm::cmderr_t [NrHarts-1:0] cmderror_i;
logic [NrHarts-1:0] cmdbusy_i;
logic [dm::ProgBufSize-1:0][31:0] progbuf_o;
assign hartinfo_i = ariane_pkg::DebugHartInfo;
dm::hartinfo_t [NrHarts-1:0] hartinfo;
logic [NrHarts-1:0] halted;
logic [NrHarts-1:0] running;
logic [NrHarts-1:0] unavailable;
logic [NrHarts-1:0] havereset;
logic [NrHarts-1:0] resumeack;
logic [NrHarts-1:0] haltreq;
logic [NrHarts-1:0] resumereq;
logic [NrHarts-1:0] ackhavereset;
logic command_write;
dm::command_t command;
logic [NrHarts-1:0] set_cmderror;
dm::cmderr_t [NrHarts-1:0] cmderror;
logic [NrHarts-1:0] cmdbusy;
logic [dm::ProgBufSize-1:0][31:0] progbuf;
dm_csrs #(
.NrHarts(NrHarts)
@ -76,26 +74,53 @@ module dm_top #(
.dmi_resp_bits_data_o ( dmi_resp_bits_data_o ),
.ndmreset_o ( ndmreset_o ),
.dmactive_o ( dmactive_o ),
.hartinfo_i ( hartinfo_i ),
.halted_i ( halted_i ),
.running_i ( running_i ),
.unavailable_i ( unavailable_i ),
.havereset_i ( havereset_i ),
.resumeack_i ( resumeack_i ),
.haltreq_o ( haltreq_o ),
.resumereq_o ( resumereq_o ),
.ackhavereset_o ( ackhavereset_o ),
.command_write_o ( command_write_o ),
.command_o ( command_o ),
.set_cmderror_i ( set_cmderror_i ),
.cmderror_i ( cmderror_i ),
.cmdbusy_i ( cmdbusy_i ),
.progbuf_o ( progbuf_o )
.hartinfo_i ( hartinfo ),
.halted_i ( halted ),
.running_i ( running ),
.unavailable_i ( unavailable ),
.havereset_i ( havereset ),
.resumeack_i ( resumeack ),
.haltreq_o ( haltreq ),
.resumereq_o ( resumereq ),
.ackhavereset_o ( ackhavereset ),
.command_write_o ( command_write ),
.command_o ( command ),
.set_cmderror_i ( set_cmderror ),
.cmderror_i ( cmderror ),
.cmdbusy_i ( cmdbusy ),
.progbuf_o ( progbuf )
);
// Debug Ctrl
logic [NrHarts-1:0] ackhalt;
// Debug Ctrl for each hart
for (genvar i = 0; i < NrHarts; i++) begin : dm_hart_ctrl
assign hartinfo[i] = ariane_pkg::DebugHartInfo;
dm_ctrl i_dm_ctrl (
.clk_i ( clk_i ),
.dmactive_i ( dmactive_o ),
.ndmreset_i ( ndmreset_o ),
.debug_req_o ( debug_req_o [i] ),
.halted_o ( halted [i] ),
.running_o ( running [i] ),
.unavailable_o ( unavailable [i] ),
.havereset_o ( havereset [i] ),
.resumeack_o ( resumeack [i] ),
.haltreq_i ( haltreq ),
.resumereq_i ( resumereq ),
.ackhavereset_i ( ackhavereset ),
.command_write_i ( command_write ),
.command_i ( command ),
.set_cmderror_o ( set_cmderror [i] ),
.cmderror_o ( cmderror [i] ),
.cmdbusy_o ( cmdbusy [i] ),
.ackhalt_i ( ackhalt [i] )
);
end
// Debug AXI Bus
assign ackhalt = '0;
assign axi_slave.aw_ready = 1'b1;
assign axi_slave.ar_ready = 1'b1;
assign axi_slave.w_ready = 1'b1;