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Fixed wrong axi signal (#2614)
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BRH 2024-11-20 10:45:21 +01:00 • committed by GitHub
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docs/01_cva6_user/AXI_Interface.rst
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@ -95,7 +95,7 @@ Table 2.1 shows the global AXI memory interface signals.
- Clock source
- | Global clock signal. Synchronous signals are sampled on the
| rising edge of the global clock.
* - **WDATA**
* - **ARESETn**
- Reset source
- | Global reset signal. This signal is active-LOW.