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Increase code coverage priv_lvl in csr_regfile (#2885)

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Co-authored-by: André Sintzoff <61976467+ASintzoff@users.noreply.github.com>
Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
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Guillaume Chauvon 2025-03-31 12:51:11 +02:00 • committed by GitHub
parent c3507a1223
commit 31dd1d232b
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1 changed files with 4 additions and 3 deletions
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7
core/csr_regfile.sv
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@ -2570,10 +2570,11 @@ module csr_regfile
priv_lvl_o != riscv::PRIV_LVL_M && v_q)
? 1'b1
: 1'b0;
end else if (CVA6Cfg.RVS) begin
assign en_translation_o = (satp_mode_is_sv && priv_lvl_o != riscv::PRIV_LVL_M) ? 1'b1 : 1'b0;
assign en_g_translation_o = 1'b0;
end else begin
assign en_translation_o = (satp_mode_is_sv && priv_lvl_o != riscv::PRIV_LVL_M)
? 1'b1
: 1'b0;
assign en_translation_o = 1'b0;
assign en_g_translation_o = 1'b0;
end
assign mxr_o = mstatus_q.mxr;