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This commit is contained in:
Florian Zaruba 2017-06-29 14:58:27 +02:00
parent 2c7beec04d
commit 31eaa9624a
4 changed files with 10 additions and 6 deletions
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2
riscv-tests

@ -1 +1 @@
Subproject commit b97a134c057c9e4b68b7735bdb7eea83360694b2
Subproject commit 2d8b8af6b0d9af136551c8f2c575a013217cb0b4

2
riscv-torture

@ -1 +1 @@
Subproject commit 6f44bec03d166432b62cab6106f62e97be153c02
Subproject commit e7566475c27db275dfc55cbbc6a5e9ec272a923c

4
tb/common/core_mem.sv
View file

@ -47,6 +47,7 @@ module core_mem (
logic [ADDRESS_WIDTH-1:0] instr_address;
logic [2:0] instr_address_offset_q;
logic [63:0] instr_data;
logic delayed_instr_request;
// D$ Mock
logic req, we;
logic [7:0] be;
@ -56,8 +57,9 @@ module core_mem (
assign data_address = {data_if_address_tag_i, index[11:3]};
assign #($urandom_range(0,40)) delayed_instr_request = instr_if_data_req_i;
// we always grant the request
assign instr_if_data_gnt_o = instr_if_data_req_i;
assign instr_if_data_gnt_o = delayed_instr_request;
assign instr_address = instr_if_address_i[ADDRESS_WIDTH-1+3:3];
// this is necessary as the interface to the dual port memory is 64 bit, but the fetch interface of the core is 32 bit
assign instr_if_data_rdata_o = (instr_address_offset_q[2]) ? instr_data[63:32] : instr_data[31:0];

8
tb/core_tb.sv
View file

@ -33,6 +33,8 @@ module core_tb;
static uvm_cmdline_processor uvcl = uvm_cmdline_processor::get_inst();
localparam int unsigned CLOCK_PERIOD = 20ns;
logic clk_i;
logic rst_ni;
logic rtc_i;
@ -156,11 +158,11 @@ module core_tb;
clk_i = 1'b0;
rst_ni = 1'b0;
repeat(8)
#10ns clk_i = ~clk_i;
#(CLOCK_PERIOD/2) clk_i = ~clk_i;
rst_ni = 1'b1;
forever begin
#10ns clk_i = 1'b1;
#10ns clk_i = 1'b0;
#(CLOCK_PERIOD/2) clk_i = 1'b1;
#(CLOCK_PERIOD/2) clk_i = 1'b0;
if (cycles > max_cycles)
$fatal(1, "Simulation reached maximum cycle count of %d", max_cycles);