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TLB lookup now features a separate register stage

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This commit is contained in:
Florian Zaruba 2017-05-07 22:53:37 +02:00
parent c62683ed32
commit 321ac41cd5
1 changed files with 17 additions and 5 deletions
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22
src/tlb.sv
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@ -61,13 +61,16 @@ module tlb #(
logic [8:0] vpn0, vpn1, vpn2;
logic [TLB_ENTRIES-1:0] lu_hit; // to replacement logic
logic [TLB_ENTRIES-1:0] replace_en; // replace the following entry, set by replacement strategy
// register signals
logic lu_access_q;
logic [63:0] lu_vaddr_q;
//-------------
// Translation
//-------------
always_comb begin : translation
vpn0 = lu_vaddr_i[20:12];
vpn1 = lu_vaddr_i[29:21];
vpn2 = lu_vaddr_i[38:30];
vpn0 = lu_vaddr_q[20:12];
vpn1 = lu_vaddr_q[29:21];
vpn2 = lu_vaddr_q[38:30];
// default assignment
lu_hit = '{default: 0};
@ -165,7 +168,7 @@ module tlb #(
// endcase
for (int unsigned i = 0; i < TLB_ENTRIES; i++) begin
// we got a hit so update the pointer as it was least recently used
if (lu_hit[i] & lu_access_i) begin
if (lu_hit[i] & lu_access_q) begin
// Set the nodes to the values we would expect
for (int unsigned lvl = 0; lvl < $clog2(TLB_ENTRIES); lvl++) begin
automatic int unsigned idx_base = $unsigned((2**lvl)-1);
@ -222,7 +225,16 @@ module tlb #(
plru_tree_q <= plru_tree_n;
end
end
// sequential process
always_ff @(posedge clk_i or negedge rst_ni) begin : proc_
if(~rst_ni) begin
lu_access_q <= 1'b0;
lu_vaddr_q <= 64'b0;
end else begin
lu_access_q <= lu_access_i;
lu_vaddr_q <= lu_vaddr_i;
end
end
//--------------
// Sanity checks
//--------------