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Set default trap vector to boot_adr + 'h40

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This commit is contained in:
Florian Zaruba 2018-07-31 01:14:53 +02:00
parent b21e43bc21
commit 3452d79fc3
2 changed files with 2 additions and 2 deletions
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2
Makefile
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@ -112,7 +112,7 @@ $(library):
# +jtag_rbb_enable=1
sim: build $(library)/ariane_dpi.so
vsim${questa_version} +permissive -64 -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
+BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=HIGH" -coverage -classdebug \
+BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=HIGH" -coverage -classdebug +jtag_rbb_enable=1 \
-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi -do " do tb/wave/wave_core.do; run -all; exit" ${top_level}_optimized +permissive-off ++$(riscv-test)
simc: build $(library)/ariane_dpi.so

2
src/csr_regfile.sv
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@ -832,7 +832,7 @@ module csr_regfile #(
// machine mode registers
mstatus_q <= 64'b0;
// set to boot address + direct mode + 4 byte offset which is the initial trap
mtvec_q <= {boot_addr_i[63:3], 3'h4};
mtvec_q <= boot_addr_i + 'h40;
medeleg_q <= 64'b0;
mideleg_q <= 64'b0;
mip_q <= 64'b0;