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csr_regfile.sv: use better signal name (CSR_MTVEC) (#2854)

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Vectored instead of misleading DirVecOnly
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André Sintzoff 2025-03-21 14:56:44 +01:00 • committed by GitHub
parent ebcb43a669
commit 38f44dad7c
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1 changed files with 5 additions and 4 deletions
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core/csr_regfile.sv
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@ -1473,12 +1473,13 @@ module csr_regfile
end
riscv::CSR_MTVEC: begin
logic DirVecOnly;
DirVecOnly = CVA6Cfg.DirectVecOnly ? 1'b0 : csr_wdata[0];
mtvec_d = {csr_wdata[CVA6Cfg.XLEN-1:2], 1'b0, DirVecOnly};
logic Vectored;
Vectored = CVA6Cfg.DirectVecOnly ? 1'b0 : csr_wdata[0];
if (!Vectored) mtvec_d = {csr_wdata[CVA6Cfg.XLEN-1:2], 1'b0, Vectored};
// we are in vector mode, this implementation requires the additional
// alignment constraint of 64 * 4 bytes
if (DirVecOnly) mtvec_d = {csr_wdata[CVA6Cfg.XLEN-1:8], 7'b0, DirVecOnly};
else
mtvec_d = {csr_wdata[CVA6Cfg.XLEN-1:8], 7'b0, Vectored};
end
riscv::CSR_MCOUNTEREN: begin
if (CVA6Cfg.RVU) mcounteren_d = {{CVA6Cfg.XLEN - 32{1'b0}}, csr_wdata[31:0]};