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https://github.com/openhwgroup/cva6.git
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Merge floating point support
This commit is contained in:
Florian Zaruba
parent
ba746f1dce
commit
3a9a0b7a58
5 changed files with 33 additions and 31 deletions
14
Makefile
14
Makefile
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@ -43,16 +43,6 @@ test_pkg := $(wildcard tb/test/*/*sequence_pkg.sv*) \
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dpi := $(patsubst tb/dpi/%.cc,work/%.o,$(wildcard tb/dpi/*.cc))
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dpi_hdr := $(wildcard tb/dpi/*.h)
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# this list contains the standalone components
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# <<<<<<< HEAD
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# src := $(wildcard src/*.sv) $(wildcard tb/common/*.sv) $(wildcard src/axi_slice/*.sv) \
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# $(wildcard src/axi_node/*.sv) $(wildcard src/axi_mem_if/src/*.sv) src/fpu_legacy/hdl/fpu_utils/fpu_ff.sv \
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# src/fpu_legacy/hdl/fpu_div_sqrt_mvp/defs_div_sqrt_mvp.sv $(wildcard src/fpu_legacy/hdl/fpu_div_sqrt_mvp/*.sv) \
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# $(fpnew_pkg) $(wildcard src/fpnew/src/utils/*.vhd) $(wildcard src/fpnew/src/ops/*.vhd) \
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# $(wildcard src/fpnew/src/subunits/*.vhd) src/fpnew/src/fpnew.vhd src/fpnew/src/fpnew_top.vhd \
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# $(filter-out src/debug/dm_pkg.sv, $(wildcard src/debug/*.sv)) $(wildcard bootrom/*.sv) \
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# $(wildcard src/debug/debug_rom/*.sv)
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# =======
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src := $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) \
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$(wildcard src/fpu/src/utils/*.vhd) \
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$(wildcard src/fpu/src/ops/*.vhd) \
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@ -160,7 +150,7 @@ $(riscv-asm-tests): build $(library)/ariane_dpi.so
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+BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
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$(QUESTASIM_FLAGS) \
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-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi \
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-do "coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" \
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-do "set StdArithNoWarnings 1; set NumericStdNoWarnings 1; coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" \
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${top_level}_optimized +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-asm-tests-$@.log
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$(riscv-benchmarks): build $(library)/ariane_dpi.so
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@ -168,7 +158,7 @@ $(riscv-benchmarks): build $(library)/ariane_dpi.so
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+BASEDIR=$(riscv-benchmarks-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
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$(QUESTASIM_FLAGS) \
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-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi \
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-do "coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" \
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-do "set StdArithNoWarnings 1; set NumericStdNoWarnings 1; coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" \
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${top_level}_optimized +permissive-off ++$(riscv-benchmarks-dir)/$@ ++$(target-options) | tee tmp/riscv-benchmarks-$@.log
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@ -149,3 +149,19 @@ rv64uf-v-fmin
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rv64uf-v-ldst
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rv64uf-v-move
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rv64uf-v-recoding
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rv64ud-p-fadd
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rv64ud-p-fclass
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rv64ud-p-fcmp
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rv64ud-p-fcvt
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rv64ud-p-fcvt_w
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rv64ud-p-fdiv
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rv64ud-p-fmadd
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rv64ud-p-fmin
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rv64ud-v-fadd
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rv64ud-v-fclass
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rv64ud-v-fcmp
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rv64ud-v-fcvt
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rv64ud-v-fcvt_w
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rv64ud-v-fdiv
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rv64ud-v-fmadd
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rv64ud-v-fmin
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@ -367,11 +367,11 @@ module ariane #(
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.lsu_exception_o ( lsu_exception_ex_id ),
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.no_st_pending_o ( no_st_pending_ex_commit ),
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// MULT
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// .mult_ready_o ( mult_ready_ex_id ),
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// .mult_valid_i ( mult_valid_id_ex ),
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// .mult_trans_id_o ( mult_trans_id_ex_id ),
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// .mult_result_o ( mult_result_ex_id ),
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// .mult_valid_o ( mult_valid_ex_id ),
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.mult_ready_o ( mult_ready_ex_id ),
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.mult_valid_i ( mult_valid_id_ex ),
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.mult_trans_id_o ( mult_trans_id_ex_id ),
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.mult_result_o ( mult_result_ex_id ),
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.mult_valid_o ( mult_valid_ex_id ),
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// FPU
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.fpu_ready_o ( fpu_ready_ex_id ),
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.fpu_valid_i ( fpu_valid_id_ex ),
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@ -405,12 +405,6 @@ module ariane #(
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.asid_i ( asid_csr_ex ), // from CSR
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.icache_areq_i ( icache_areq_cache_ex ),
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.icache_areq_o ( icache_areq_ex_cache ),
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.mult_ready_o ( mult_ready_ex_id ),
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.mult_valid_i ( mult_valid_id_ex ),
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.mult_trans_id_o ( mult_trans_id_ex_id ),
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.mult_result_o ( mult_result_ex_id ),
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.mult_valid_o ( mult_valid_ex_id ),
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// DCACHE interfaces
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.dcache_req_ports_i ( dcache_req_ports_cache_ex ),
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.dcache_req_ports_o ( dcache_req_ports_ex_cache )
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@ -331,8 +331,8 @@ module load_unit (
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// prepare these signals for faster selection in the next cycle
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assign signed_d = load_data_q.operator inside { LW, LH, LB };
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assign fp_sign_d = load_data_q.operator inside { FLW, FLH, FLB };
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assign signed_d = load_data_d.operator inside {LW, LH, LB};
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assign fp_sign_d = load_data_d.operator inside {FLW, FLH, FLB};
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assign idx_d = (load_data_d.operator inside {LW, FLW}) ? load_data_d.address_offset + 3 :
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(load_data_d.operator inside {LH, FLH}) ? load_data_d.address_offset + 1 :
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load_data_d.address_offset;
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@ -354,15 +354,15 @@ module load_unit (
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// result mux
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always_comb begin
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unique case (load_data_q.operator)
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LW, LWU: result_o = {{32{sign_bit}}, shifted_data[31:0]};
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LH, LHU: result_o = {{48{sign_bit}}, shifted_data[15:0]};
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LB, LBU: result_o = {{56{sign_bit}}, shifted_data[7:0]};
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LW, LWU, FLW: result_o = {{32{sign_bit}}, shifted_data[31:0]};
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LH, LHU, FLH: result_o = {{48{sign_bit}}, shifted_data[15:0]};
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LB, LBU, FLB: result_o = {{56{sign_bit}}, shifted_data[7:0]};
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default: result_o = shifted_data;
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endcase
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end
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always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
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if(~rst_ni) begin
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if (~rst_ni) begin
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idx_q <= 0;
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signed_q <= 0;
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fp_sign_q <= 0;
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@ -5,8 +5,8 @@ add wave -noupdate -group frontend -group icache /ariane_tb/dut/i_ariane/i_std_c
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add wave -noupdate -group frontend -group ras /ariane_tb/dut/i_ariane/i_frontend/i_ras/*
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add wave -noupdate -group frontend -group btb /ariane_tb/dut/i_ariane/i_frontend/i_btb/*
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add wave -noupdate -group frontend -group bht /ariane_tb/dut/i_ariane/i_frontend/i_bht/*
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add wave -noupdate -group frontend -group instr_scan /ariane_tb/dut/i_ariane/i_frontend/*/i_instr_scan/*
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add wave -noupdate -group frontend -group fetch_fifo /ariane_tb/dut/i_ariane/i_frontend/i_fetch_fifo/*
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# add wave -noupdate -group frontend -group instr_scan /ariane_tb/dut/i_ariane/i_frontend/*/i_instr_scan/*
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# add wave -noupdate -group frontend -group fetch_fifo /ariane_tb/dut/i_ariane/i_frontend/i_fetch_fifo/*
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add wave -noupdate -group id_stage -group decoder /ariane_tb/dut/i_ariane/id_stage_i/decoder_i/*
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add wave -noupdate -group id_stage -group compressed_decoder /ariane_tb/dut/i_ariane/id_stage_i/compressed_decoder_i/*
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@ -22,6 +22,8 @@ add wave -noupdate -group ex_stage -group alu /ariane_tb/dut/i_ariane/ex_stage_i
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add wave -noupdate -group ex_stage -group mult /ariane_tb/dut/i_ariane/ex_stage_i/i_mult/*
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add wave -noupdate -group ex_stage -group mult -group mul /ariane_tb/dut/i_ariane/ex_stage_i/i_mult/i_mul/*
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add wave -noupdate -group ex_stage -group mult -group div /ariane_tb/dut/i_ariane/ex_stage_i/i_mult/i_div/*
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add wave -noupdate -group ex_stage -group fpu /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/*
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add wave -noupdate -group ex_stage -group fpu -group fpnew /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/*
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add wave -noupdate -group ex_stage -group lsu /ariane_tb/dut/i_ariane/ex_stage_i/lsu_i/*
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add wave -noupdate -group ex_stage -group lsu -group lsu_bypass /ariane_tb/dut/i_ariane/ex_stage_i/lsu_i/lsu_bypass_i/*
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