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Functional coverage : Add cross to illegal and exception coverage models (#1839)
This commit is contained in:
Jalali
GitHub
parent
b4c287a18e
commit
3d7e417bce
9 changed files with 345 additions and 95 deletions
65
verif/env/uvme/cov/uvme_exception_covg.sv
vendored
65
verif/env/uvme/cov/uvme_exception_covg.sv
vendored
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@ -24,7 +24,8 @@ covergroup cg_exception(
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bit unaligned_access_supported,
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bit mode_u_supported,
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bit mode_s_supported,
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bit debug_supported
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bit debug_supported,
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bit [CSR_MASK_WL-1:0] cfg_illegal_csr
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) with function sample (
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uvma_isacov_instr_c instr
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);
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@ -86,6 +87,65 @@ covergroup cg_exception(
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}
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cp_is_ebreak: coverpoint instr.name {
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bins is_ebreak = {uvma_isacov_pkg::EBREAK,
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uvma_isacov_pkg::C_EBREAK};
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}
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cp_is_dret: coverpoint instr.name {
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bins is_dret = {uvma_isacov_pkg::DRET};
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}
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cp_is_ecall: coverpoint instr.name {
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bins is_ecall = {uvma_isacov_pkg::ECALL};
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}
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cp_is_csr: coverpoint instr.group {
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bins is_csr_instr = {uvma_isacov_pkg::CSR_GROUP};
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}
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cp_illegal_csr: coverpoint instr.csr {
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bins UNSUPPORTED_CSR[] = {[uvma_isacov_pkg::USTATUS:uvma_isacov_pkg::VLENB]} with (cfg_illegal_csr[item] == 1) iff(instr.trap);
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}
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cp_misalign_load: coverpoint instr.group {
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bins misalign_load = {uvma_isacov_pkg::MISALIGN_LOAD_GROUP};
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}
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cp_misalign_store: coverpoint instr.group {
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bins misalign_store = {uvma_isacov_pkg::MISALIGN_STORE_GROUP};
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}
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cp_add_mem: coverpoint instr.rvfi.mem_addr[1:0] {
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bins add_mem[] = {[0:$]};
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}
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cross_breakpoint : cross cp_exception, cp_is_ebreak {
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ignore_bins IGN = !binsof(cp_exception) intersect{3};
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}
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cross_ecall : cross cp_exception, cp_is_ecall {
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ignore_bins IGN = !binsof(cp_exception) intersect{11};
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}
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cross_dret : cross cp_exception, cp_is_dret iff(!debug_supported){
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ignore_bins IGN = !binsof(cp_exception) intersect{2};
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}
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cross_illegal_csr : cross cp_exception, cp_illegal_csr, cp_is_csr {
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ignore_bins IGN = !binsof(cp_exception) intersect{2};
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}
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cross_misaligned_load : cross cp_exception, cp_misalign_load, cp_add_mem iff(!unaligned_access_supported){
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ignore_bins IGN_EXC = !binsof(cp_exception) intersect{4};
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ignore_bins IGN_ADD = binsof(cp_add_mem) intersect{0};
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}
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cross_misaligned_store : cross cp_exception, cp_misalign_store, cp_add_mem iff(!unaligned_access_supported){
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ignore_bins IGN_EXC = !binsof(cp_exception) intersect{6};
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ignore_bins IGN_ADD = binsof(cp_add_mem) intersect{0};
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}
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endgroup : cg_exception
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class uvme_exception_cov_model_c extends uvm_component;
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@ -133,7 +193,8 @@ function void uvme_exception_cov_model_c::build_phase(uvm_phase phase);
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.unaligned_access_supported(cfg.unaligned_access_supported),
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.mode_u_supported(cfg.mode_u_supported),
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.mode_s_supported(cfg.mode_s_supported),
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.debug_supported(cfg.debug_supported));
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.debug_supported(cfg.debug_supported),
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.cfg_illegal_csr(cfg.unsupported_csr_mask));
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mon_trn_fifo = new("mon_trn_fifo" , this);
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30
verif/env/uvme/cov/uvme_illegal_instr_covg.sv
vendored
30
verif/env/uvme/cov/uvme_illegal_instr_covg.sv
vendored
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@ -40,6 +40,14 @@ covergroup cg_illegal_i(
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bins ILLEGAL_NOPCODE_FUNCT7[3] = {[0:$]} with (!(item inside legal_i_funct7)) iff (!(instr.rvfi.insn[6:0] inside legal_i_opcode)); //with the wrong opcode
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}
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cp_is_illegal: coverpoint instr.cause {
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bins ILLEGAL_INSTR = {2};
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}
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cross_exc_illegal_0 : cross cp_illegal_opcode, cp_is_illegal;
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cross_exc_illegal_1 : cross cp_illegal_funct3, cp_is_illegal;
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cross_exc_illegal_2 : cross cp_illegal_funct7, cp_is_illegal;
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endgroup : cg_illegal_i
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covergroup cg_illegal_m(
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@ -64,6 +72,14 @@ covergroup cg_illegal_m(
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bins ILLEGAL_NOPCODE_FUNCT7[3] = {[0:$]} with (item != 7'b0000001) iff (instr.rvfi.insn[6:0] != 7'b0110011); //with the wrong opcode
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}
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cp_is_illegal: coverpoint instr.cause {
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bins ILLEGAL_INSTR = {2};
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}
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cross_exc_illegal_0 : cross cp_illegal_opcode, cp_is_illegal;
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cross_exc_illegal_1 : cross cp_illegal_funct3, cp_is_illegal;
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cross_exc_illegal_2 : cross cp_illegal_funct7, cp_is_illegal;
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endgroup : cg_illegal_m
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covergroup cg_illegal_zicsr(
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@ -83,6 +99,13 @@ covergroup cg_illegal_zicsr(
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bins ILLEGAL_NOPCODE_FUNCT3 = {0,4} iff (instr.rvfi.insn[6:0] != 7'b1110011); //with the wrong opcode
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}
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cp_is_illegal: coverpoint instr.cause {
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bins ILLEGAL_INSTR = {2};
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}
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cross_exc_illegal_0 : cross cp_illegal_opcode, cp_is_illegal;
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cross_exc_illegal_1 : cross cp_illegal_funct3, cp_is_illegal;
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endgroup : cg_illegal_zicsr
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covergroup cg_illegal_zifencei(
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@ -102,6 +125,13 @@ covergroup cg_illegal_zifencei(
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bins ILLEGAL_NOPCODE_FUNCT3[3] = {[0:$]} with (item != 7'b001) iff (instr.rvfi.insn[6:0] != 7'b0001111); //with the wrong opcode
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}
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cp_is_illegal: coverpoint instr.cause {
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bins ILLEGAL_INSTR = {2};
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}
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cross_exc_illegal_0 : cross cp_illegal_opcode, cp_is_illegal;
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cross_exc_illegal_1 : cross cp_illegal_funct3, cp_is_illegal;
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endgroup : cg_illegal_zifencei
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class uvme_illegal_instr_cov_model_c extends uvm_component;
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47
verif/env/uvme/uvme_cva6_cfg.sv
vendored
47
verif/env/uvme/uvme_cva6_cfg.sv
vendored
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@ -48,6 +48,9 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
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// Zicond extension
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rand bit ext_zicond_supported;
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//pmp entries
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rand int nr_pmp_entries;
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`uvm_object_utils_begin(uvme_cva6_cfg_c)
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`uvm_field_int ( enabled , UVM_DEFAULT )
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`uvm_field_enum(uvm_active_passive_enum, is_active , UVM_DEFAULT )
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@ -55,6 +58,7 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
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`uvm_field_int ( cov_model_enabled , UVM_DEFAULT )
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`uvm_field_int ( trn_log_enabled , UVM_DEFAULT )
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`uvm_field_int ( ext_zicond_supported , UVM_DEFAULT )
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`uvm_field_int ( nr_pmp_entries , UVM_DEFAULT )
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`uvm_field_int ( sys_clk_period , UVM_DEFAULT + UVM_DEC)
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`uvm_field_object(clknrst_cfg, UVM_DEFAULT)
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@ -115,7 +119,8 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
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mode_s_supported == 0;
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mode_u_supported == 0;
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pmp_supported == 0;
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pmp_supported == 1;
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nr_pmp_entries == 16;
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debug_supported == 0;
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unaligned_access_supported == 0;
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@ -138,6 +143,15 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
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}
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}
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constraint pmp_const {
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if (!pmp_supported) {
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nr_pmp_entries == 0;
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}
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else {
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nr_pmp_entries inside {0, 16, 64};
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}
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}
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constraint default_cva6_boot_cons {
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(!mhartid_plusarg_valid) -> (mhartid == 'h0000_0000);
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(!mimpid_plusarg_valid) -> (mimpid == 'h0000_0000);
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@ -255,9 +269,38 @@ function void uvme_cva6_cfg_c::set_unsupported_csr_mask();
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super.set_unsupported_csr_mask();
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// Remove unsupported CSRs for Embedded configuration
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unsupported_csr_mask[uvma_core_cntrl_pkg::MCOUNTINHIBIT] = 1;
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unsupported_csr_mask[uvma_core_cntrl_pkg::MTVAL] = 1;
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// Add supported CSRs for Embedded configuration
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for (int i = 0; i < MAX_NUM_HPMCOUNTERS; i++) begin
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unsupported_csr_mask[uvma_core_cntrl_pkg::MHPMEVENT3+i] = 0;
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unsupported_csr_mask[uvma_core_cntrl_pkg::MHPMCOUNTER3+i] = 0;
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unsupported_csr_mask[uvma_core_cntrl_pkg::MHPMCOUNTER3H+i] = 0;
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end
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unsupported_csr_mask[uvma_core_cntrl_pkg::MSTATUSH] = 0;
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unsupported_csr_mask[uvma_core_cntrl_pkg::CYCLE] = 0;
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unsupported_csr_mask[uvma_core_cntrl_pkg::INSTRET] = 0;
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unsupported_csr_mask[uvma_core_cntrl_pkg::CYCLEH] = 0;
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unsupported_csr_mask[uvma_core_cntrl_pkg::INSTRETH] = 0;
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// Exist but only-read zero in embedded application
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unsupported_csr_mask[uvma_core_cntrl_pkg::MCOUNTINHIBIT] = 0;
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// Remove unsupported pmp CSRs
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if (nr_pmp_entries == 0) begin
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unsupported_csr_mask[uvma_core_cntrl_pkg::PMPCFG0+:16] = 16'hffff;
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unsupported_csr_mask[uvma_core_cntrl_pkg::PMPADDR0+:64] = 64'hffffffffffffffff;
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end
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else if (nr_pmp_entries == 16) begin
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unsupported_csr_mask[uvma_core_cntrl_pkg::PMPCFG4+:12] = 12'hfff;
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unsupported_csr_mask[uvma_core_cntrl_pkg::PMPADDR16+:48] = 48'hffffffffffff;
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end
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else if (nr_pmp_entries == 64) begin //if pmp entries is 64 we support all the pmp CSRs
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unsupported_csr_mask[uvma_core_cntrl_pkg::PMPCFG0+:16] = 16'h0;
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unsupported_csr_mask[uvma_core_cntrl_pkg::PMPADDR0+:64] = 64'h0;
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end
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endfunction : set_unsupported_csr_mask
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`endif // __UVME_CVA6_CFG_SV__
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@ -615,8 +615,17 @@ plan "CVA6 Verification Master Plan";
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feature "Illegal instructions";
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weight = 1;
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Comment = "RVFI limitation issue(#1338)";
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measure Group illegal_instructions;
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source = "group: uvme_cva6_pkg::cg_illegal_i", "group: uvme_cva6_pkg::cg_illegal_m", "group: uvme_cva6_pkg::cg_illegal_zicsr", "group: uvme_cva6_pkg::cg_illegal_zifencei";
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measure Group ILLEGAL_I_EXT;
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source = "group instance: uvme_cva6_pkg.uvme_cva6_pkg.illegal_i_cg";
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endmeasure
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measure Group ILLEGAL_ZICSR_EXT;
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source = "group instance: uvme_cva6_pkg.uvme_cva6_pkg.illegal_zicsr_cg";
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endmeasure
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measure Group ILLEGAL_ZIFENCEI_EXT;
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source = "group instance: uvme_cva6_pkg.uvme_cva6_pkg.illegal_zifencei_cg";
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endmeasure
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measure Group ILLEGAL_M_EXT;
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source = "group instance: uvme_cva6_pkg.uvme_cva6_pkg.illegal_m_cg";
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endmeasure
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endfeature
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endfeature
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@ -1287,7 +1296,7 @@ plan "CVA6 Verification Master Plan";
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endfeature
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feature Exceptions;
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measure Group Exceptions;
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source = "group: uvme_cva6_pkg::cg_exception::SHAPE{Guard_ON(cp_exception.IGN_ACCESS_FAULT_EXC,cp_exception.IGN_DEBUG_REQUEST,cp_exception.IGN_ENV_CALL_SMODE,cp_exception.IGN_ENV_CALL_UMODE),Guard_OFF(cp_exception.IGN_ADDR_MISALIGNED_EXC)}";
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source = "group instance: uvme_cva6_pkg.uvme_cva6_pkg.exception_cg";
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endmeasure
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endfeature
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endfeature
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@ -211,95 +211,23 @@ module uvmt_cva6_tb;
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uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_tdata3_vif%0d", i), .value(rvfi_csr_if[i]));
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uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_tinfo_vif%0d", i), .value(rvfi_csr_if[i]));
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uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_tcontrol_vif%0d", i), .value(rvfi_csr_if[i]));
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uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent3_vif%0d", i), .value(rvfi_csr_if[i]));
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uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent4_vif%0d", i), .value(rvfi_csr_if[i]));
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uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent5_vif%0d", i), .value(rvfi_csr_if[i]));
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uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent6_vif%0d", i), .value(rvfi_csr_if[i]));
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uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent7_vif%0d", i), .value(rvfi_csr_if[i]));
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uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent8_vif%0d", i), .value(rvfi_csr_if[i]));
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uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent9_vif%0d", i), .value(rvfi_csr_if[i]));
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uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent10_vif%0d", i), .value(rvfi_csr_if[i]));
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uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent11_vif%0d", i), .value(rvfi_csr_if[i]));
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uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent12_vif%0d", i), .value(rvfi_csr_if[i]));
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uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent13_vif%0d", i), .value(rvfi_csr_if[i]));
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uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent14_vif%0d", i), .value(rvfi_csr_if[i]));
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uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent15_vif%0d", i), .value(rvfi_csr_if[i]));
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uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent16_vif%0d", i), .value(rvfi_csr_if[i]));
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uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent17_vif%0d", i), .value(rvfi_csr_if[i]));
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uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent18_vif%0d", i), .value(rvfi_csr_if[i]));
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uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent19_vif%0d", i), .value(rvfi_csr_if[i]));
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uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent20_vif%0d", i), .value(rvfi_csr_if[i]));
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uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent21_vif%0d", i), .value(rvfi_csr_if[i]));
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uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent22_vif%0d", i), .value(rvfi_csr_if[i]));
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uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent23_vif%0d", i), .value(rvfi_csr_if[i]));
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uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent24_vif%0d", i), .value(rvfi_csr_if[i]));
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uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent25_vif%0d", i), .value(rvfi_csr_if[i]));
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uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent26_vif%0d", i), .value(rvfi_csr_if[i]));
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uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent27_vif%0d", i), .value(rvfi_csr_if[i]));
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uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent28_vif%0d", i), .value(rvfi_csr_if[i]));
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uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent28_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent29_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent30_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent31_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter3_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter4_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter5_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter6_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter7_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter8_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter9_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter10_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter11_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter12_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter13_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter14_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter15_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter16_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter17_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter18_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter19_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter20_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter21_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter22_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter23_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter24_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter25_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter26_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter27_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter28_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter29_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter30_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter31_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter3h_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter4h_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter5h_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter6h_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter7h_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter8h_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter9h_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter10h_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter11h_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter12h_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter13h_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter14h_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter15h_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter16h_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter17h_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter18h_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter19h_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter20h_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter21h_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter22h_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter23h_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter24h_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter25h_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter26h_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter27h_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter28h_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter29h_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter30h_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter31h_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
for (int j = 3; j < 32; j++) begin
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent%0d_vif%0d", j, i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter%0d_vif%0d", j, i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter%0dh_vif%0d", j, i), .value(rvfi_csr_if[i]));
|
||||
end
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mconfigptr_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_cycle_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_cycleh_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_instret_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_instreth_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
for (int j = 0; j < 16; j++) begin
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_pmpcfg%0d_vif%0d", j, i), .value(rvfi_csr_if[i]));
|
||||
end
|
||||
for (int j = 0; j < 64; j++) begin
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_pmpaddr%0d_vif%0d", j, i), .value(rvfi_csr_if[i]));
|
||||
end
|
||||
|
||||
end
|
||||
end
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -5840,4 +5840,61 @@ csrcs:
|
|||
#MHPMEVENT20 read value
|
||||
csrr x14, 0x334
|
||||
|
||||
##########################
|
||||
#MCOUNTINHBIT testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h4}
|
||||
##########################
|
||||
#MCOUNTINHBIT Write clear/set value 0x1f
|
||||
li x3, 0xffffffe0
|
||||
csrrc x14, 0x320, x3
|
||||
li x3, 0x1f
|
||||
csrrs x14, 0x320, x3
|
||||
|
||||
#MCOUNTINHBIT read value
|
||||
csrr x14, 0x320
|
||||
|
||||
#MCOUNTINHBIT Write clear/set value 0x0
|
||||
li x3, 0xffffffff
|
||||
csrrc x14, 0x320, x3
|
||||
li x3, 0x0
|
||||
csrrs x14, 0x320, x3
|
||||
|
||||
#MCOUNTINHBIT read value
|
||||
csrr x14, 0x320
|
||||
|
||||
#MCOUNTINHBIT Write clear/set value 0x15
|
||||
li x3, 0xffffffea
|
||||
csrrc x14, 0x320, x3
|
||||
li x3, 0x15
|
||||
csrrs x14, 0x320, x3
|
||||
|
||||
#MCOUNTINHBIT read value
|
||||
csrr x14, 0x320
|
||||
|
||||
#MCOUNTINHBIT Write clear/set value 0xa
|
||||
li x3, 0xfffffff5
|
||||
csrrc x14, 0x320, x3
|
||||
li x3, 0xa
|
||||
csrrs x14, 0x320, x3
|
||||
|
||||
#MCOUNTINHBIT read value
|
||||
csrr x14, 0x320
|
||||
|
||||
#MCOUNTINHBIT Write clear/set value 0x4
|
||||
li x3, 0xfffffffb
|
||||
csrrc x14, 0x320, x3
|
||||
li x3, 0x4
|
||||
csrrs x14, 0x320, x3
|
||||
|
||||
#MCOUNTINHBIT read value
|
||||
csrr x14, 0x320
|
||||
|
||||
#MCOUNTINHBIT Write clear/set value 0x4
|
||||
li x19, 0xfffffffb
|
||||
csrrc x19, 0x320, x19
|
||||
li x3, 0x4
|
||||
csrrs x19, 0x320, x19
|
||||
|
||||
#MCOUNTINHBIT read value
|
||||
csrr x14, 0x320
|
||||
|
||||
ret
|
||||
|
|
|
|||
|
|
@ -4630,4 +4630,49 @@ csrcsi:
|
|||
#MHPMEVENT9 read value
|
||||
csrr x14, 0x329
|
||||
|
||||
##########################
|
||||
#MCOUNTINHBIT testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h6}
|
||||
##########################
|
||||
#MCOUNTINHBIT Write clear/set value 0x1f
|
||||
csrrci x14, 0x320, 0x0
|
||||
csrrsi x14, 0x320, 0x1f
|
||||
|
||||
#MCOUNTINHBIT read value
|
||||
csrr x14, 0x320
|
||||
|
||||
#MCOUNTINHBIT Write clear/set value 0x0
|
||||
csrrci x14, 0x320, 0x1f
|
||||
csrrsi x14, 0x320, 0x0
|
||||
|
||||
#MCOUNTINHBIT read value
|
||||
csrr x14, 0x320
|
||||
|
||||
#MCOUNTINHBIT Write clear/set value 0x15
|
||||
csrrci x14, 0x320, 0xa
|
||||
csrrsi x14, 0x320, 0x15
|
||||
|
||||
#MCOUNTINHBIT read value
|
||||
csrr x14, 0x320
|
||||
|
||||
#MCOUNTINHBIT Write clear/set value 0xa
|
||||
csrrci x14, 0x320, 0x15
|
||||
csrrsi x14, 0x320, 0xa
|
||||
|
||||
#MCOUNTINHBIT read value
|
||||
csrr x14, 0x320
|
||||
|
||||
#MCOUNTINHBIT Write clear/set value 0x6
|
||||
csrrci x14, 0x320, 0x19
|
||||
csrrsi x14, 0x320, 0x6
|
||||
|
||||
#MCOUNTINHBIT read value
|
||||
csrr x14, 0x320
|
||||
|
||||
#MCOUNTINHBIT Write clear/set value 0x6
|
||||
csrrci x0, 0x320, 0x19
|
||||
csrrsi x0, 0x320, 0x6
|
||||
|
||||
#MCOUNTINHBIT read value
|
||||
csrr x14, 0x320
|
||||
|
||||
ret
|
||||
|
|
|
|||
|
|
@ -4630,4 +4630,42 @@ csrrw:
|
|||
#MHPMCOUNTERH14 read value
|
||||
csrr x14, 0xb8e
|
||||
|
||||
##########################
|
||||
#MCOUNTINHBIT testing W/R values '{'hffffffff, 'h0, 'h55555555, 'haaaaaaaa, 'h9683580}
|
||||
##########################
|
||||
#MCOUNTINHBIT Write value 0xffffffff
|
||||
li x3, 0xffffffff
|
||||
csrw 0X320, x3
|
||||
|
||||
#MCOUNTINHBIT read value
|
||||
csrr x14, 0X320
|
||||
|
||||
#MCOUNTINHBIT Write value 0x0
|
||||
li x3, 0x0
|
||||
csrw 0X320, x3
|
||||
|
||||
#MCOUNTINHBIT read value
|
||||
csrr x14, 0X320
|
||||
|
||||
#MCOUNTINHBIT Write value 0x55555555
|
||||
li x3, 0x55555555
|
||||
csrw 0X320, x3
|
||||
|
||||
#MCOUNTINHBIT read value
|
||||
csrr x14, 0X320
|
||||
|
||||
#MCOUNTINHBIT Write value 0xaaaaaaaa
|
||||
li x3, 0xaaaaaaaa
|
||||
csrw 0X320, x3
|
||||
|
||||
#MCOUNTINHBIT read value
|
||||
csrr x14, 0X320
|
||||
|
||||
#MCOUNTINHBIT Write value 0x9683580
|
||||
li x3, 0x9683580
|
||||
csrw 0X320, x3
|
||||
|
||||
#MCOUNTINHBIT read value
|
||||
csrr x14, 0X320
|
||||
|
||||
ret
|
||||
|
|
|
|||
|
|
@ -4025,4 +4025,43 @@ csrrwi:
|
|||
#MHPMEVENT31 read value
|
||||
csrr x14, 0x33f
|
||||
|
||||
##########################
|
||||
#MCOUNTINHBIT testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h1}
|
||||
##########################
|
||||
#MCOUNTINHBIT Write immediate value 0x1f
|
||||
csrrwi x14, 0x320, 0x1f
|
||||
|
||||
#MCOUNTINHBIT read value
|
||||
csrr x14, 0x320
|
||||
|
||||
#MCOUNTINHBIT Write immediate value 0x0
|
||||
csrrwi x14, 0x320, 0x0
|
||||
|
||||
#MCOUNTINHBIT read value
|
||||
csrr x14, 0x320
|
||||
|
||||
#MCOUNTINHBIT Write immediate value 0x15
|
||||
csrrwi x14, 0x320, 0x15
|
||||
|
||||
#MCOUNTINHBIT read value
|
||||
csrr x14, 0x320
|
||||
|
||||
#MCOUNTINHBIT Write immediate value 0xa
|
||||
csrrwi x14, 0x320, 0xa
|
||||
|
||||
#MCOUNTINHBIT read value
|
||||
csrr x14, 0x320
|
||||
|
||||
#MCOUNTINHBIT Write immediate value 0x1
|
||||
csrrwi x14, 0x320, 0x1
|
||||
|
||||
#MCOUNTINHBIT read value
|
||||
csrr x14, 0x320
|
||||
|
||||
#MCOUNTINHBIT Write immediate value 0x1
|
||||
csrrwi x0, 0x320, 0x1
|
||||
|
||||
#MCOUNTINHBIT read value
|
||||
csrr x14, 0x320
|
||||
|
||||
ret
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue