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update verif/.gitignore

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Côme Allart 2023-08-24 15:40:13 +02:00
parent 437b3ec556
commit 437734ccd0
1 changed files with 19 additions and 19 deletions
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verif/.gitignore vendored
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@ -35,25 +35,25 @@ waves.shm/
*.log
stdout.txt
.vscode
cva6/tests/riscv-compliance/
cva6/tests/riscv-arch-test/
cva6/tests/riscv-tests/
cva6/tests/riscv-isa-sim/
cva6/sim/dv/
cva6/sim/vcs_results
cva6/sim/verilator_work
cva6/sim/out_*
cva6/sim/Mem_init.txt
cva6/sim/*.txt
cva6/sim/trace*
cva6/sim/simv*
cva6/sim/ucli.key
cva6/sim/.inter*
cva6/sim/.vcs*
cva6/sim/inter*
cva6/sim/novas*
cva6/sim/verdiLog
cva6/sim/Verdi.ses*
tests/riscv-compliance/
tests/riscv-arch-test/
tests/riscv-tests/
tests/riscv-isa-sim/
sim/dv/
sim/vcs_results
sim/verilator_work
sim/out_*
sim/Mem_init.txt
sim/*.txt
sim/trace*
sim/simv*
sim/ucli.key
sim/.inter*
sim/.vcs*
sim/inter*
sim/novas*
sim/verdiLog
sim/Verdi.ses*
riviera_results/
*/vendor_lib/dpi_dasm_spike/
*/vendor_lib/verilab/svlib/