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document issue stage (#2598)
* Fill docs/design/design-manual/source/cva6_issue_stage.adoc * Add variables to docs/design/design-manual/source/design.adoc * Update port doc comments in core/issue_stage.sv, core/issue_read_operands.sv and core/scoreboard.sv
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@ -33,63 +33,63 @@ module issue_read_operands
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input logic clk_i,
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// Asynchronous reset active low - SUBSYSTEM
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input logic rst_ni,
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// Flush - CONTROLLER
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// Prevent from issuing - CONTROLLER
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input logic flush_i,
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// Stall inserted by Acc dispatcher - ACC_DISPATCHER
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input logic stall_i,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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// Entry about the instruction to issue - SCOREBOARD
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input scoreboard_entry_t [CVA6Cfg.NrIssuePorts-1:0] issue_instr_i,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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// Instruction to issue - SCOREBOARD
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input logic [CVA6Cfg.NrIssuePorts-1:0][31:0] orig_instr_i,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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// Is there an instruction to issue - SCOREBOARD
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input logic [CVA6Cfg.NrIssuePorts-1:0] issue_instr_valid_i,
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// Issue stage acknowledge - TO_BE_COMPLETED
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// Issue stage acknowledge - SCOREBOARD
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output logic [CVA6Cfg.NrIssuePorts-1:0] issue_ack_o,
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// Forwarding - SCOREBOARD
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input forwarding_t fwd_i,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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// FU data useful to execute instruction - EX_STAGE
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output fu_data_t [CVA6Cfg.NrIssuePorts-1:0] fu_data_o,
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// Unregistered version of fu_data_o.operanda - TO_BE_COMPLETED
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// Unregistered version of fu_data_o.operanda - EX_STAGE
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output logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rs1_forwarding_o,
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// Unregistered version of fu_data_o.operandb - TO_BE_COMPLETED
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// Unregistered version of fu_data_o.operandb - EX_STAGE
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output logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rs2_forwarding_o,
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// Instruction pc - TO_BE_COMPLETED
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// Program Counter - EX_STAGE
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output logic [CVA6Cfg.VLEN-1:0] pc_o,
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// Is compressed instruction - TO_BE_COMPLETED
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// Is compressed instruction - EX_STAGE
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output logic is_compressed_instr_o,
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// Fixed Latency Unit ready to accept new request - TO_BE_COMPLETED
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// Fixed Latency Unit is ready - EX_STAGE
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input logic flu_ready_i,
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// ALU output is valid - TO_BE_COMPLETED
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// ALU output is valid - EX_STAGE
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output logic [CVA6Cfg.NrIssuePorts-1:0] alu_valid_o,
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// Branch instruction is valid - TO_BE_COMPLETED
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// Branch unit is valid - EX_STAGE
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output logic [CVA6Cfg.NrIssuePorts-1:0] branch_valid_o,
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// Transformed instruction - TO_BE_COMPLETED
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// Transformed trap instruction - EX_STAGE
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output logic [CVA6Cfg.NrIssuePorts-1:0][31:0] tinst_o,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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// Information of branch prediction - EX_STAGE
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output branchpredict_sbe_t branch_predict_o,
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// Load Store Unit is ready - TO_BE_COMPLETED
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// Load store unit FU is ready - EX_STAGE
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input logic lsu_ready_i,
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// Load Store Unit result is valid - TO_BE_COMPLETED
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// Load store unit FU is valid - EX_STAGE
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output logic [CVA6Cfg.NrIssuePorts-1:0] lsu_valid_o,
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// Mult result is valid - TO_BE_COMPLETED
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// Mult FU is valid - EX_STAGE
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output logic [CVA6Cfg.NrIssuePorts-1:0] mult_valid_o,
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// FPU is ready - TO_BE_COMPLETED
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// FPU FU is ready - EX_STAGE
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input logic fpu_ready_i,
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// FPU result is valid - TO_BE_COMPLETED
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// FPU FU is valid - EX_STAGE
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output logic [CVA6Cfg.NrIssuePorts-1:0] fpu_valid_o,
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// FPU fmt field from instruction - TO_BE_COMPLETED
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// FPU fmt field - EX_STAGE
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output logic [1:0] fpu_fmt_o,
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// FPU rm field from isntruction - TO_BE_COMPLETED
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// FPU rm field - EX_STAGE
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output logic [2:0] fpu_rm_o,
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// ALU output is valid - TO_BE_COMPLETED
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// ALU2 FU is valid - EX_STAGE
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output logic [CVA6Cfg.NrIssuePorts-1:0] alu2_valid_o,
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// CSR result is valid - TO_BE_COMPLETED
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// CSR is valid - EX_STAGE
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output logic [CVA6Cfg.NrIssuePorts-1:0] csr_valid_o,
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// CVXIF result is valid - TO_BE_COMPLETED
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// CVXIF FU is valid - EX_STAGE
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output logic [CVA6Cfg.NrIssuePorts-1:0] cvxif_valid_o,
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// CVXIF is ready - TO_BE_COMPLETED
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// CVXIF is FU ready - EX_STAGE
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input logic cvxif_ready_i,
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// CVXIF offloaded instruction - TO_BE_COMPLETED
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// CVXIF offloader instruction value - EX_STAGE
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output logic [31:0] cvxif_off_instr_o,
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// CVA6 Hart ID - SUBSYSTEM
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input logic [CVA6Cfg.XLEN-1:0] hart_id_i,
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@ -110,16 +110,16 @@ module issue_read_operands
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output logic x_transaction_rejected_o,
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output logic x_issue_writeback_o,
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output logic [CVA6Cfg.TRANS_ID_BITS-1:0] x_id_o,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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// Destination register in the register file - COMMIT_STAGE
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input logic [CVA6Cfg.NrCommitPorts-1:0][4:0] waddr_i,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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// Value to write to register file - COMMIT_STAGE
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input logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0] wdata_i,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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// GPR write enable - COMMIT_STAGE
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input logic [CVA6Cfg.NrCommitPorts-1:0] we_gpr_i,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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// FPR write enable - COMMIT_STAGE
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input logic [CVA6Cfg.NrCommitPorts-1:0] we_fpr_i,
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// Stall signal, we do not want to fetch any more entries - TO_BE_COMPLETED
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// Issue stall - PERF_COUNTERS
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output logic stall_issue_o
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);
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@ -35,9 +35,9 @@ module issue_stage
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input logic rst_ni,
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// Is scoreboard full - PERF_COUNTERS
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output logic sb_full_o,
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// TO_BE_COMPLETED - CONTROLLER
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// Prevent from issuing - CONTROLLER
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input logic flush_unissued_instr_i,
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// TO_BE_COMPLETED - CONTROLLER
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// Flush whole scoreboard - CONTROLLER
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input logic flush_i,
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// Stall inserted by Acc dispatcher - ACC_DISPATCHER
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input logic stall_i,
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@ -65,7 +65,7 @@ module issue_stage
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output logic [CVA6Cfg.NrIssuePorts-1:0][31:0] tinst_o,
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// Fixed Latency Unit is ready - EX_STAGE
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input logic flu_ready_i,
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// ALU FU is valid - EX_STAGE
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// ALU output is valid - EX_STAGE
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output logic [CVA6Cfg.NrIssuePorts-1:0] alu_valid_o,
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// Branch unit is valid - EX_STAGE
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output logic [CVA6Cfg.NrIssuePorts-1:0] branch_valid_o,
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@ -125,25 +125,25 @@ module issue_stage
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output logic issue_instr_hs_o,
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// Transaction ID - EX_STAGE
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input logic [CVA6Cfg.NrWbPorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] trans_id_i,
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// The branch engine uses the write back from the ALU - EX_STAGE
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// Result from branch unit - EX_STAGE
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input bp_resolve_t resolved_branch_i,
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// TO_BE_COMPLETED - EX_STAGE
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// Results to write back - EX_STAGE
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input logic [CVA6Cfg.NrWbPorts-1:0][CVA6Cfg.XLEN-1:0] wbdata_i,
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// exception from execute stage or CVXIF - EX_STAGE
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input exception_t [CVA6Cfg.NrWbPorts-1:0] ex_ex_i,
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// TO_BE_COMPLETED - EX_STAGE
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// Indicates valid results - EX_STAGE
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input logic [CVA6Cfg.NrWbPorts-1:0] wt_valid_i,
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// CVXIF write enable - EX_STAGE
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input logic x_we_i,
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// CVXIF destination register - ISSUE_STAGE
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// CVXIF destination register - EX_STAGE
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input logic [4:0] x_rd_i,
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// TO_BE_COMPLETED - EX_STAGE
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// Destination register in register file - COMMIT_STAGE
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input logic [CVA6Cfg.NrCommitPorts-1:0][4:0] waddr_i,
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// TO_BE_COMPLETED - EX_STAGE
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// Value to write to register file - COMMIT_STAGE
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input logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0] wdata_i,
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// GPR write enable - EX_STAGE
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// GPR write enable - COMMIT_STAGE
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input logic [CVA6Cfg.NrCommitPorts-1:0] we_gpr_i,
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// FPR write enable - EX_STAGE
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// FPR write enable - COMMIT_STAGE
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input logic [CVA6Cfg.NrCommitPorts-1:0] we_fpr_i,
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// Instructions to commit - COMMIT_STAGE
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output scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_o,
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@ -25,68 +25,68 @@ module scoreboard #(
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input logic clk_i,
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// Asynchronous reset active low - SUBSYSTEM
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input logic rst_ni,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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// Is scoreboard full - PERF_COUNTERS
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output logic sb_full_o,
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// Flush only un-issued instructions - TO_BE_COMPLETED
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// Prevent from issuing - CONTROLLER
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input logic flush_unissued_instr_i,
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// Flush whole scoreboard - TO_BE_COMPLETED
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// Flush whole scoreboard - CONTROLLER
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input logic flush_i,
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// Writeback Handling of CVXIF
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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// TO_BE_COMPLETED - ISSUE_READ_OPERANDS
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input logic x_transaction_accepted_i,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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// TO_BE_COMPLETED - ISSUE_READ_OPERANDS
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input logic x_issue_writeback_i,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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// TO_BE_COMPLETED - ISSUE_READ_OPERANDS
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input logic [CVA6Cfg.TRANS_ID_BITS-1:0] x_id_i,
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// advertise instruction to commit stage, if commit_ack_i is asserted advance the commit pointer
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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// Instructions to commit - COMMIT_STAGE
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output scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_o,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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// Instruction is cancelled - COMMIT_STAGE
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output logic [CVA6Cfg.NrCommitPorts-1:0] commit_drop_o,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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// Commit acknowledge - COMMIT_STAGE
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input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i,
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// instruction to put on top of scoreboard e.g.: top pointer
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// we can always put this instruction to the top unless we signal with asserted full_o
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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// Handshake's data with decode stage - ID_STAGE
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input scoreboard_entry_t [CVA6Cfg.NrIssuePorts-1:0] decoded_instr_i,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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// instruction value - ID_STAGE
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input logic [CVA6Cfg.NrIssuePorts-1:0][31:0] orig_instr_i,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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// Handshake's valid with decode stage - ID_STAGE
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input logic [CVA6Cfg.NrIssuePorts-1:0] decoded_instr_valid_i,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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// Handshake's acknowlege with decode stage - ID_STAGE
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output logic [CVA6Cfg.NrIssuePorts-1:0] decoded_instr_ack_o,
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// instruction to issue logic, if issue_instr_valid and issue_ready is asserted, advance the issue pointer
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// Issue scoreboard entry - ACC_DISPATCHER
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// Entry about the instruction to issue - ISSUE_READ_OPERANDS
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output scoreboard_entry_t [CVA6Cfg.NrIssuePorts-1:0] issue_instr_o,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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// Instruction to issue - ISSUE_READ_OPERANDS
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output logic [CVA6Cfg.NrIssuePorts-1:0][31:0] orig_instr_o,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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// Is there an instruction to issue - ISSUE_READ_OPERANDS
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output logic [CVA6Cfg.NrIssuePorts-1:0] issue_instr_valid_o,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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// Issue stage acknowledge - ISSUE_READ_OPERANDS
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input logic [CVA6Cfg.NrIssuePorts-1:0] issue_ack_i,
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// Forwarding - issue_read_operands
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// Forwarding - ISSUE_READ_OPERANDS
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output forwarding_t fwd_o,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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// Result from branch unit - EX_STAGE
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input bp_resolve_t resolved_branch_i,
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// Transaction ID at which to write the result back - TO_BE_COMPLETED
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// Transaction ID at which to write the result back - EX_STAGE
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input logic [CVA6Cfg.NrWbPorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] trans_id_i,
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// Results to write back - TO_BE_COMPLETED
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// Results to write back - EX_STAGE
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input logic [CVA6Cfg.NrWbPorts-1:0][CVA6Cfg.XLEN-1:0] wbdata_i,
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// Exception from a functional unit (e.g.: ld/st exception) - TO_BE_COMPLETED
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// Exception from a functional unit (e.g.: ld/st exception) - EX_STAGE
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input exception_t [CVA6Cfg.NrWbPorts-1:0] ex_i,
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// Indicates valid results - TO_BE_COMPLETED
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// Indicates valid results - EX_STAGE
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input logic [CVA6Cfg.NrWbPorts-1:0] wt_valid_i,
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// Cvxif we for writeback - TO_BE_COMPLETED
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// Cvxif we for writeback - EX_STAGE
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input logic x_we_i,
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// CVXIF destination register - ISSUE_STAGE
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input logic [4:0] x_rd_i,
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// TO_BE_COMPLETED - RVFI
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// Issue pointer - RVFI
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output logic [ CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] rvfi_issue_pointer_o,
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// TO_BE_COMPLETED - RVFI
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// Commit pointer - RVFI
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output logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] rvfi_commit_pointer_o
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);
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@ -16,21 +16,31 @@ ISSUE_STAGE Module
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Description
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^^^^^^^^^^^
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The execution can be roughly divided into four parts: issue(1), read
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operands(2), execute(3) and write-back(4). The ISSUE_STAGE module
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handles step one, two and four. The ISSUE_STAGE module receives the
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decoded instructions and issues them to the various functional units.
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ISSUE_STAGE issues instructions (1), reorders their results (2) and sends completed instructions in-order to COMMIT_STAGE (3).
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A data structure called scoreboard is used to keep track of data related
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to the issue instruction: which functional unit and which destination
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register they are. The scoreboard handle the write-back data received
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from the COMMIT_STAGE module.
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(1) ISSUE_STAGE issues instructions in-order.
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It makes sure that instructions from ID_STAGE have everything they need to run.
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It waits until all requirements are met.
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Once an instruction is ready to run, ISSUE_STAGE sends it to EX_STAGE with its operands.
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Furthermore it contains the CPU’s register file.
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(2) ISSUE_STAGE reorders instructions results.
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It gets results of instruction executions out-of-order from EX_STAGE.
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ISSUE_STAGE stores these results reordered.
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(3) ISSUE_STAGE sends completed instructions in-order to COMMIT_STAGE.
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This is where architectural state is modified.
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Scoreboard module keeps track of instructions and their results.
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Issue_read_operands module contains all the issue logic and the register file.
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The module is connected to:
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* TO BE COMPLETED
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* CONTROLLER module can request to flush the pipeline buffer at the end of ISSUE_STAGE.
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CONTROLLER module can also request to flush the whole Scoreboard.
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* ID_STAGE module delivers decoded instructions to ISSUE_STAGE.
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* EX_STAGE module gets instructions issued by ISSUE_STAGE to execute them.
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EX_STAGE module also returns results to ISSUE_STAGE.
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* COMMIT_STAGE module delivers ISSUE_STAGE clearance to remove the oldest instruction from Scoreboard.
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include::port_issue_stage.adoc[]
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@ -38,7 +48,23 @@ include::port_issue_stage.adoc[]
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Functionality
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^^^^^^^^^^^^^
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TO BE COMPLETED
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ISSUE_STAGE has three functionalities.
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(1) ISSUE_STAGE issues instructions.
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Instructions from ID_STAGE are sent to Scoreboard module, which forwards them to Issue_read_operands module.
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Issue_read_operands queries Scoreboard module for data dependences (Scoreboard is also able to return forwarded values) and gets the list of busy functional units from EX_STAGE.
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Issue_read_operands sends to EX_STAGE the instructions to execute and acknowledges to Scoreboard so that it stores them: the instruction is issued.
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Issued instructions are acknowledged to ID_STAGE.
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Each of these steps can block its successors.
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The flush signal from CONTROLLER module is also sent to Scoreboard module to prevent from issuing.
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Instructions are issued in-order: an instruction cannot be issued unless all its predecessors are issued.
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(2) ISSUE_STAGE reorders instructions results.
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Results from EX_STAGE are sent to Scoreboard module so that they are stored.
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(3) ISSUE_STAGE sends completed instructions in-order to COMMIT_STAGE.
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The oldest instructions from Scoreboard are exposed to COMMIT_STAGE.
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When COMMIT_STAGE acknowledges a commit, the committed instruction is removed from Scoreboard and the register file in Issue_read_operands is updated with the instruction result.
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[[issue_stage-submodules]]
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Submodules
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@ -50,9 +76,53 @@ image:issue_stage_modules.png[ISSUE_STAGE submodules]
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Scoreboard
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++++++++++
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||||
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||||
The scoreboard contains a FIFO to store the decoded instructions. Issued
|
||||
instruction is pushed to the FIFO if it is not full. It indicates which
|
||||
registers are going to be clobbered by a previously issued instruction.
|
||||
Scoreboard contains a FIFO which contains an entry for each issued instruction.
|
||||
Each entry is removed once the instruction is committed.
|
||||
Instruction results are inserted into Scoreboard when they are ready.
|
||||
The FIFO is flushed when requested by CONTROLLER.
|
||||
|
||||
Scoreboard is used in all three functionalities of ISSUE_STAGE.
|
||||
|
||||
(1) ISSUE_STAGE issues instructions.
|
||||
Up to {issue-width} instruction(s) can be received from ID_STAGE each cycle.
|
||||
They are transmitted to Issue_read_operands with incremental transaction IDs which wrap at {NrScoreboardEntries}.
|
||||
The result buses and Scoreboard entries are also transmitted to Issue_read_operands for it to detect data dependences and perform operand forwarding.
|
||||
When Issue_read_operands acknowledges an instruction, it is inserted into the FIFO.
|
||||
|
||||
Scoreboard has a capacity of {NrScoreboardEntries} entries.
|
||||
Instructions which would make Scoreboard overflow are not transmitted to Issue_read_operands (ISSUE_STAGE stalls).
|
||||
|
||||
The flush signal from CONTROLLER module removes all entries from the Scoreboard and prevents from issuing.
|
||||
The transaction ID of the next issued instruction is 0.
|
||||
|
||||
(2) ISSUE_STAGE reorders instructions results.
|
||||
Results are returned from functional units in the EX_STAGE to Scoreboard via result buses, with their transaction IDs.
|
||||
Scoreboard stores this result into the entry associated with this transaction ID.
|
||||
If an exception is returned, it is stored too.
|
||||
ifeval::[{SpeculativeSb} == true]
|
||||
If the result is a branch miss, the speculative instructions following it are cancelled.
|
||||
endif::[]
|
||||
|
||||
ifeval::[{RVZCMP} == true]
|
||||
FIXME Document behavior related to macro instructions
|
||||
endif::[]
|
||||
|
||||
ifeval::[{DebugEn} == true]
|
||||
FIXME Document behavior related to debug
|
||||
endif::[]
|
||||
|
||||
ifeval::[{CvxifEn} == true]
|
||||
FIXME Document behavior related to CV-X-IF
|
||||
endif::[]
|
||||
|
||||
ifeval::[{FpPresent} == true]
|
||||
FIXME Document behavior related to FPU
|
||||
endif::[]
|
||||
|
||||
(3) ISSUE_STAGE sends completed instructions in-order to COMMIT_STAGE.
|
||||
Each of the {commit-width} oldest entry(ies) in Scoreboard are exposed to COMMIT_STAGE, one per commit port.
|
||||
This makes commit happen in-order.
|
||||
When COMMIT_STAGE acknowledges on a commit port, the entry is removed from Scoreboard.
|
||||
|
||||
include::port_scoreboard.adoc[]
|
||||
|
||||
|
|
@ -60,6 +130,118 @@ include::port_scoreboard.adoc[]
|
|||
Issue_read_operands
|
||||
+++++++++++++++++++
|
||||
|
||||
TO BE COMPLETED
|
||||
Issue_read_operands tracks hazards and gets the input operands for the instructions to execute.
|
||||
The following hazards can prevent instructions from being issued.
|
||||
|
||||
* Data hazards: ISSUE_STAGE checks that the instruction operands are available.
|
||||
|
||||
** [[raw_hazard]] Read-After-Write (RAW): if one of the source registers of the instruction to issue is the destination register of one of the instructions in the Scoreboard, issue is blocked.
|
||||
However, CVA6 implements operand forwarding: instead of blocking the instruction, the operand is taken from either +
|
||||
a) a functional unit which returns a result which is not an exception, with a transaction ID which points to a Scoreboard entry whose destination register is the requested source register; +
|
||||
b) a Scoreboard entry whose destination register is the requested source register has a result which is not an exception. +
|
||||
Forwarding is not possible from CSR instructions.
|
||||
ifeval::[{RVS} == true]
|
||||
FIXME Document behavior related to SFENCE_VMA
|
||||
endif::[]
|
||||
+
|
||||
ifeval::[{SuperscalarEn} == true]
|
||||
The instruction in the second issue port is not issued when one of its source registers is the destination register of the instruction in the first issue port.
|
||||
No operand forwarding is possible between the two issue ports.
|
||||
endif::[]
|
||||
|
||||
** Write-After-Write (WAW): if the instruction to issue has the same destination register as one of the instructions in the Scoreboard, issue is blocked.
|
||||
Instructions being committed are ignored because the will not be in the scoreboard anymore since the next cycle.
|
||||
+
|
||||
ifeval::[{SuperscalarEn} == true]
|
||||
The instruction in the second issue port is not issued when it has the same destination register as the instruction in the first issue port.
|
||||
endif::[]
|
||||
|
||||
** Special case: there are no data hazards on `x0`.
|
||||
|
||||
ifeval::[{SpeculativeSb} == true]
|
||||
** Cancelled instructions are ignored by the hazard detection mechanism.
|
||||
endif::[]
|
||||
|
||||
ifeval::[{CvxifEn} == true]
|
||||
** FIXME hazards related to CV-X-IF
|
||||
endif::[]
|
||||
|
||||
* Structural hazards: ISSUE_STAGE checks that a functional unit (FU) and its result bus (RB) are ready to execute the instruction.
|
||||
|
||||
** Integer division instructions and some^[FIXME{sp}which?]^ CSR instructions have an unknown latency.
|
||||
When EX_STAGE reports that such an instruction is running, instructions using ALU, BRANCH, CSR or MULT are blocked.
|
||||
This is to avoid conflicts on the RB shared by these four FUs.
|
||||
ifeval::[{SuperscalarEn} == true]
|
||||
Note that ALU2 might still be available.
|
||||
endif::[]
|
||||
|
||||
** Multiplications have a fixed latency of 2 cycles.
|
||||
Instructions using ALU, BRANCH or CSR are blocked if an instruction using MULT was issued one cycle earlier.
|
||||
This is to avoid conflicts on the RB shared by these four FUs.
|
||||
ifeval::[{SuperscalarEn} == true]
|
||||
Note that ALU2 might still be available.
|
||||
endif::[]
|
||||
Instructions using MULT are not blocked because the multiplier is pipelined and can accept one instruction each cycle.
|
||||
|
||||
ifeval::[{FpPresent} == true]
|
||||
** FIXME hazards related to FPU
|
||||
endif::[]
|
||||
|
||||
** Instructions using LSU are blocked if LSU is not ready.
|
||||
|
||||
ifeval::[{SuperscalarEn} == true]
|
||||
** The second issue port cannot issue instructions using CSR.
|
||||
|
||||
ifeval::[{CvxifEn} == true]
|
||||
** The second issue port cannot issue instructions using CV-X-IF.
|
||||
endif::[]
|
||||
|
||||
** The second issue port cannot issue an instruction using a FU when the first port issues an instruction using the same FU.
|
||||
This is because a FU can only accept one instruction each cycle.
|
||||
|
||||
** When both ALU and ALU2 are available, ALU instructions use ALU2.
|
||||
|
||||
** The second issue port cannot issue an instruction using ALU, BRANCH or CSR when the first issue port is issuing an instruction using ALU, BRANCH or CSR.
|
||||
This is to avoid conflicts on the RB shared by these four FUs.
|
||||
Note that ALU2 might still be available.
|
||||
|
||||
* Control hazards: ISSUE_STAGE checks that no instruction is executed speculatively while it must not.
|
||||
|
||||
** The second issue port is completely blocked when the first port issues an instruction using CSR.
|
||||
|
||||
** The second issue port
|
||||
ifeval::[{SpeculativeSb} == true]
|
||||
cannot issue an instruction using LSU
|
||||
endif::[]
|
||||
ifeval::[{SpeculativeSb} == false]
|
||||
is completely blocked
|
||||
endif::[]
|
||||
when the first issue port issues an instruction using BRANCH, unless it is a JAL.
|
||||
|
||||
// {SuperscalarEn} == true
|
||||
endif::[]
|
||||
|
||||
Data hazards are ignored when an exception occurred earlier in the pipeline.
|
||||
As no FU is involved, there are no structural hazards either.
|
||||
|
||||
Instructions are issued in-order, which means that when an instruction makes ISSUE_STAGE stall, next instructions are blocked.
|
||||
ifeval::[{SuperscalarEn} == true]
|
||||
As a consequence, it is not possible to issue the instruction in the second issue port when the instruction in the first issue port is blocked.
|
||||
endif::[]
|
||||
|
||||
ifeval::[{SuperscalarEn} == true]
|
||||
However, it is possible that the instruction in the first issue port is issued while the instruction in the second issue port is not.
|
||||
In such case, ID_STAGE moves the instruction in the second issue port to the first issue port so that it is issued next.
|
||||
endif::[]
|
||||
|
||||
The input operands provided to EX_STAGE come from the register file by default.
|
||||
However, when one of the source registers has a RAW dependence, the corresponding input operand is replaced by the forwarded value (see <<raw_hazard,Data hazards/RAW hazards>> above).
|
||||
The register file is an instance of `ariane_regfile` where ach register stores {XLEN} bits and the register at index 0 is wired to zero.
|
||||
|
||||
ifeval::[{CvxifEn} == true]
|
||||
FIXME Document behavior related to CV-X-IF
|
||||
endif::[]
|
||||
|
||||
Instructions are sent to EX_STAGE via a register so they are visible in EX_STAGE one cycle after being issued.
|
||||
|
||||
include::port_issue_read_operands.adoc[]
|
||||
|
|
|
|||
|
|
@ -15,11 +15,31 @@ ifeval::[{SuperscalarEn} == true]
|
|||
:ifetch-len: 64
|
||||
:instr-per-fetch: 4
|
||||
:issue-width: 2
|
||||
:commit-width: 2
|
||||
endif::[]
|
||||
ifeval::[{SuperscalarEn} == false]
|
||||
:ifetch-len: 32
|
||||
:instr-per-fetch: 2
|
||||
:issue-width: 1
|
||||
:commit-width: {NrCommmitPorts}
|
||||
endif::[]
|
||||
:SpeculativeSb: {SuperscalarEn}
|
||||
|
||||
:FpPresent: false
|
||||
ifeval::[{RVF} == true]
|
||||
:FpPresent: true
|
||||
endif::[]
|
||||
ifeval::[{RVD} == true]
|
||||
:FpPresent: true
|
||||
endif::[]
|
||||
ifeval::[{XF16} == true]
|
||||
:FpPresent: true
|
||||
endif::[]
|
||||
ifeval::[{XF16ALT} == true]
|
||||
:FpPresent: true
|
||||
endif::[]
|
||||
ifeval::[{XF8} == true]
|
||||
:FpPresent: true
|
||||
endif::[]
|
||||
|
||||
[[DesignDocument]]
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue