mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-20 12:17:19 -04:00
Add regular behavioral RAM, no interface
This commit is contained in:
Florian Zaruba
parent
baf51e5354
commit
48587017ac
5 changed files with 142 additions and 100 deletions
6
Makefile
6
Makefile
|
|
@ -63,11 +63,13 @@ build-agents: ${agents}
|
|||
build-interfaces: ${interfaces}
|
||||
vlog${questa_version} ${compile_flag} -work ${library} -incr ${interfaces} ${list_incdir} -suppress 2583
|
||||
|
||||
# Run the specified test case
|
||||
sim:
|
||||
# vsim${questa_version} ${top_level}_optimized -c -do "run -a"
|
||||
vsim${questa_version} -lib ${library} ${top_level}_optimized +UVM_TESTNAME=${test_case} -coverage -classdebug -do "do tb/wave/wave_core.do"
|
||||
|
||||
simc:
|
||||
vsim${questa_version} -c -lib ${library} ${top_level}_optimized +UVM_TESTNAME=${test_case} -coverage -classdebug -do "do tb/wave/wave_core.do"
|
||||
|
||||
# Run the specified test case
|
||||
$(tests):
|
||||
# Optimize top level
|
||||
vopt${questa_version} -work ${library} ${compile_flag} $@_tb -o $@_tb_optimized +acc -check_synthesis
|
||||
|
|
|
|||
|
|
@ -39,5 +39,46 @@ module core_mem (
|
|||
output logic data_if_data_rvalid_o,
|
||||
output logic [63:0] data_if_data_rdata_o
|
||||
);
|
||||
// we always grant the access
|
||||
assign instr_if_data_gnt_o = instr_if_data_req_i;
|
||||
localparam ADDRESS_WIDTH = 11;
|
||||
|
||||
logic [ADDRESS_WIDTH-1:0] instr_address;
|
||||
logic [2:0] instr_address_offset_q;
|
||||
|
||||
assign instr_address = instr_if_address_i[ADDRESS_WIDTH-1+3:3];
|
||||
|
||||
logic [63:0] instr_data;
|
||||
|
||||
assign instr_if_data_rdata_o = (instr_address_offset_q[2]) ? instr_data[63:32] : instr_data[31:0];
|
||||
|
||||
dp_ram #(
|
||||
.ADDR_WIDTH ( ADDRESS_WIDTH ),
|
||||
.DATA_WIDTH ( 64 )
|
||||
) ram_i (
|
||||
.clk ( clk_i ),
|
||||
.en_a_i ( 1'b1 ),
|
||||
.addr_a_i ( instr_address ),
|
||||
.wdata_a_i ( ), // not connected
|
||||
.rdata_a_o ( instr_data ),
|
||||
.we_a_i ( 1'b0 ), // r/o interface
|
||||
.be_a_i ( ),
|
||||
.en_b_i ( ),
|
||||
.addr_b_i ( ),
|
||||
.wdata_b_i ( ),
|
||||
.rdata_b_o ( ),
|
||||
.we_b_i ( ),
|
||||
.be_b_i ( )
|
||||
);
|
||||
|
||||
|
||||
always_ff @(posedge clk_i or negedge rst_ni) begin : proc_
|
||||
if(~rst_ni) begin
|
||||
instr_if_data_rvalid_o <= 1'b0;
|
||||
instr_address_offset_q <= 'b0;
|
||||
end else begin
|
||||
instr_if_data_rvalid_o <= instr_if_data_req_i;
|
||||
instr_address_offset_q <= instr_if_address_i[2:0];
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -10,59 +10,50 @@
|
|||
|
||||
module dp_ram
|
||||
#(
|
||||
parameter ADDR_WIDTH = 8
|
||||
parameter int ADDR_WIDTH = 8,
|
||||
parameter int DATA_WIDTH = 64
|
||||
)(
|
||||
// Clock and Reset
|
||||
input logic clk,
|
||||
input logic clk,
|
||||
|
||||
input logic en_a_i,
|
||||
input logic [ADDR_WIDTH-1:0] addr_a_i,
|
||||
input logic [31:0] wdata_a_i,
|
||||
output logic [31:0] rdata_a_o,
|
||||
input logic we_a_i,
|
||||
input logic [3:0] be_a_i,
|
||||
input logic en_a_i,
|
||||
input logic [ADDR_WIDTH-1:0] addr_a_i,
|
||||
input logic [DATA_WIDTH-1:0] wdata_a_i,
|
||||
output logic [DATA_WIDTH-1:0] rdata_a_o,
|
||||
input logic we_a_i,
|
||||
input logic [DATA_WIDTH/8-1:0] be_a_i,
|
||||
|
||||
input logic en_b_i,
|
||||
input logic [ADDR_WIDTH-1:0] addr_b_i,
|
||||
input logic [31:0] wdata_b_i,
|
||||
output logic [31:0] rdata_b_o,
|
||||
input logic we_b_i,
|
||||
input logic [3:0] be_b_i
|
||||
input logic en_b_i,
|
||||
input logic [ADDR_WIDTH-1:0] addr_b_i,
|
||||
input logic [DATA_WIDTH-1:0] wdata_b_i,
|
||||
output logic [DATA_WIDTH-1:0] rdata_b_o,
|
||||
input logic we_b_i,
|
||||
input logic [DATA_WIDTH/8-1:0] be_b_i
|
||||
);
|
||||
|
||||
localparam words = 2**ADDR_WIDTH;
|
||||
localparam words = 2**ADDR_WIDTH;
|
||||
|
||||
logic [3:0][7:0] mem[words];
|
||||
logic [DATA_WIDTH/8-1:0][7:0] mem [words-1:0];
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (en_a_i && we_a_i)
|
||||
begin
|
||||
if (be_a_i[0])
|
||||
mem[addr_a_i][0] <= wdata_a_i[7:0];
|
||||
if (be_a_i[1])
|
||||
mem[addr_a_i][1] <= wdata_a_i[15:8];
|
||||
if (be_a_i[2])
|
||||
mem[addr_a_i][2] <= wdata_a_i[23:16];
|
||||
if (be_a_i[3])
|
||||
mem[addr_a_i][3] <= wdata_a_i[31:24];
|
||||
always @(posedge clk) begin
|
||||
|
||||
if (en_a_i && we_a_i) begin
|
||||
for (int i = 0; i < DATA_WIDTH/8; i++) begin
|
||||
if (be_a_i[i])
|
||||
mem[addr_a_i][i] <= wdata_a_i[i +: 8];
|
||||
end
|
||||
end
|
||||
|
||||
rdata_a_o <= mem[addr_a_i];
|
||||
|
||||
if (en_b_i && we_b_i) begin
|
||||
for (int i = 0; i < DATA_WIDTH/8; i++) begin
|
||||
if (be_b_i[i])
|
||||
mem[addr_b_i][i] <= wdata_b_i[i +: 8];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
rdata_a_o <= mem[addr_a_i];
|
||||
|
||||
if (en_b_i && we_b_i)
|
||||
begin
|
||||
if (be_b_i[0])
|
||||
mem[addr_b_i][0] <= wdata_b_i[7:0];
|
||||
if (be_b_i[1])
|
||||
mem[addr_b_i][1] <= wdata_b_i[15:8];
|
||||
if (be_b_i[2])
|
||||
mem[addr_b_i][2] <= wdata_b_i[23:16];
|
||||
if (be_b_i[3])
|
||||
mem[addr_b_i][3] <= wdata_b_i[31:24];
|
||||
end
|
||||
|
||||
rdata_b_o <= mem[addr_b_i];
|
||||
end
|
||||
// output port two combinatorially since we need to mimic a cache interface
|
||||
assign rdata_b_o = mem[addr_b_i];
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
112
tb/core_tb.sv
112
tb/core_tb.sv
|
|
@ -21,6 +21,44 @@ module core_tb;
|
|||
debug_if debug_if();
|
||||
core_if core_if(clk_i);
|
||||
|
||||
|
||||
logic [63:0] instr_if_address;
|
||||
logic instr_if_data_req;
|
||||
logic [3:0] instr_if_data_be;
|
||||
logic instr_if_data_gnt;
|
||||
logic instr_if_data_rvalid;
|
||||
logic [31:0] instr_if_data_rdata;
|
||||
|
||||
logic [63:0] data_if_address_i;
|
||||
logic [63:0] data_if_data_wdata_i;
|
||||
logic data_if_data_req_i;
|
||||
logic data_if_data_we_i;
|
||||
logic [7:0] data_if_data_be_i;
|
||||
logic [1:0] data_if_tag_status_i;
|
||||
logic data_if_data_gnt_o;
|
||||
logic data_if_data_rvalid_o;
|
||||
logic [63:0] data_if_data_rdata_o;
|
||||
|
||||
core_mem core_mem_i (
|
||||
.clk_i ( clk_i ),
|
||||
.rst_ni ( rst_ni ),
|
||||
.instr_if_address_i ( instr_if_address ),
|
||||
.instr_if_data_req_i ( instr_if_data_req ),
|
||||
.instr_if_data_be_i ( instr_if_data_be ),
|
||||
.instr_if_data_gnt_o ( instr_if_data_gnt ),
|
||||
.instr_if_data_rvalid_o ( instr_if_data_rvalid ),
|
||||
.instr_if_data_rdata_o ( instr_if_data_rdata ),
|
||||
.data_if_address_i ( data_if_address_i ),
|
||||
.data_if_data_wdata_i ( data_if_data_wdata_i ),
|
||||
.data_if_data_req_i ( data_if_data_req_i ),
|
||||
.data_if_data_we_i ( data_if_data_we_i ),
|
||||
.data_if_data_be_i ( data_if_data_be_i ),
|
||||
.data_if_tag_status_i ( data_if_tag_status_i ),
|
||||
.data_if_data_gnt_o ( data_if_data_gnt_o ),
|
||||
.data_if_data_rvalid_o ( data_if_data_rvalid_o ),
|
||||
.data_if_data_rdata_o ( data_if_data_rdata_o )
|
||||
);
|
||||
|
||||
ariane dut (
|
||||
.clk_i ( clk_i ),
|
||||
.rst_ni ( rst_ni ),
|
||||
|
|
@ -33,12 +71,12 @@ module core_tb;
|
|||
.core_id_i ( core_if.core_id ),
|
||||
.cluster_id_i ( core_if.cluster_id ),
|
||||
|
||||
.instr_if_address_o ( instr_if.address ),
|
||||
.instr_if_data_req_o ( instr_if.data_req ),
|
||||
.instr_if_data_be_o ( instr_if.data_be[3:0] ),
|
||||
.instr_if_data_gnt_i ( instr_if.data_gnt & instr_if.data_req ),
|
||||
.instr_if_data_rvalid_i ( instr_if.data_rvalid ),
|
||||
.instr_if_data_rdata_i ( instr_if.data_rdata[31:0] ),
|
||||
.instr_if_address_o ( instr_if_address ),
|
||||
.instr_if_data_req_o ( instr_if_data_req ),
|
||||
.instr_if_data_be_o ( instr_if_data_be ),
|
||||
.instr_if_data_gnt_i ( instr_if_data_gnt ),
|
||||
.instr_if_data_rvalid_i ( instr_if_data_rvalid ),
|
||||
.instr_if_data_rdata_i ( instr_if_data_rdata ),
|
||||
|
||||
.data_if_address_o ( data_if.address ),
|
||||
.data_if_data_wdata_o ( data_if.data_wdata ),
|
||||
|
|
@ -79,6 +117,19 @@ module core_tb;
|
|||
#10ns clk_i = ~clk_i;
|
||||
end
|
||||
|
||||
task preload_memories();
|
||||
logic [7:0] rmem [0:1024];
|
||||
|
||||
$display("Reading memory");
|
||||
$readmemh("test/add_test.v", rmem, 0);
|
||||
|
||||
for (int i = 0; i < 1024/8; i++) begin
|
||||
for (int j = 0; j < 8; j++)
|
||||
core_mem_i.ram_i.mem[i][j] = rmem[i*8 + j];
|
||||
end
|
||||
|
||||
endtask : preload_memories
|
||||
|
||||
program testbench (core_if core_if, mem_if instr_if);
|
||||
initial begin
|
||||
uvm_config_db #(virtual core_if)::set(null, "uvm_test_top", "core_if", core_if);
|
||||
|
|
@ -88,53 +139,10 @@ module core_tb;
|
|||
// Start UVM test
|
||||
run_test();
|
||||
end
|
||||
// logic [7:0] imem [400];
|
||||
// logic [63:0] address [$];
|
||||
// logic [63:0] addr;
|
||||
// // instruction memory
|
||||
// initial begin
|
||||
// // read mem file
|
||||
// $readmemh("add_test.v", imem, 64'b0);
|
||||
// $display("Read instruction memory file");
|
||||
// instr_if.mck.data_rdata <= 32'b0;
|
||||
// // apply stimuli for instruction interface
|
||||
// forever begin
|
||||
// // instr_if.mck.data_rvalid <= 1'b0;
|
||||
// // instr_if.mck.data_gnt <= 1'b0;
|
||||
|
||||
// @(instr_if.mck)
|
||||
// instr_if.mck.data_rvalid <= 1'b0;
|
||||
// fork
|
||||
// imem_read: begin
|
||||
// // instr_if.mck.data_rvalid <= 1'b0;
|
||||
// if (instr_if.data_req) begin
|
||||
// address.push_back(instr_if.mck.address);
|
||||
// end
|
||||
// end
|
||||
|
||||
// imem_write: begin
|
||||
// if (address.size() != 0) begin
|
||||
// instr_if.mck.data_rvalid <= 1'b1;
|
||||
// addr = address.pop_front();
|
||||
// instr_if.mck.data_rdata <= {
|
||||
// imem[$unsigned(addr + 3)],
|
||||
// imem[$unsigned(addr + 2)],
|
||||
// imem[$unsigned(addr + 1)],
|
||||
// imem[$unsigned(addr + 0)]
|
||||
// };
|
||||
// $display("Address: %0h, Data: %0h", addr, {
|
||||
// imem[$unsigned(addr + 3)],
|
||||
// imem[$unsigned(addr + 2)],
|
||||
// imem[$unsigned(addr + 1)],
|
||||
// imem[$unsigned(addr + 0)]
|
||||
// });
|
||||
// end else
|
||||
// instr_if.mck.data_rvalid <= 1'b0;
|
||||
// end
|
||||
// join_none
|
||||
|
||||
// end
|
||||
// end
|
||||
initial begin
|
||||
preload_memories();
|
||||
end
|
||||
endprogram
|
||||
|
||||
testbench tb(core_if, instr_if);
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ add wave -noupdate -group id_stage -group issue_read_operands /core_tb/dut/id_st
|
|||
add wave -noupdate -group id_stage /core_tb/dut/id_stage_i/*
|
||||
add wave -noupdate -group ex_stage -group ALU /core_tb/dut/ex_stage_i/alu_i/*
|
||||
add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/*
|
||||
add wave -noupdate -group ex_stage -group branch_engine /core_tb/dut/ex_stage_i/branch_engine_i/*
|
||||
add wave -noupdate -group ex_stage -group branch_unit /core_tb/dut/ex_stage_i/branch_unit_i/*
|
||||
add wave -noupdate -group ex_stage -expand -group csr_buffer /core_tb/dut/ex_stage_i/csr_buffer_i/*
|
||||
add wave -noupdate -group ex_stage /core_tb/dut/ex_stage_i/*
|
||||
add wave -noupdate -group commit_stage /core_tb/dut/commit_stage_i/*
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue