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🐛 Fix full signal and else branch of re-aligner

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This commit is contained in:
Florian Zaruba 2017-06-28 17:27:38 +02:00
parent 36db73b40b
commit 4cd7f99a07
2 changed files with 6 additions and 7 deletions
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2
src/fetch_fifo.sv
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@ -55,7 +55,7 @@ module fetch_fifo
logic [$clog2(DEPTH)-1:0] write_pointer_n, write_pointer_q;
logic [$clog2(DEPTH)-1:0] status_cnt_n, status_cnt_q; // this integer will be truncated by the synthesis tool
assign in_ready_o = !(status_cnt_q == DEPTH-2);
assign in_ready_o = (status_cnt_q < DEPTH-2);
assign full = (status_cnt_q == DEPTH);
assign empty = (status_cnt_q == '0);

11
src/instr_realigner.sv
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@ -102,10 +102,10 @@ module instr_realigner (
end
end
end
// this is a full 32 bit instruction like
// _______________________
// | instruction [31:0] |
// |______________________
// this is a full 32 bit instruction like
// _______________________
// | instruction [31:0] |
// |______________________
// we have an outstanding unaligned instruction
else if (unaligned_q) begin
@ -166,8 +166,7 @@ module instr_realigner (
end
// there can never be a whole 32 bit instruction on a half word access
end
end
end else
// ----------------------------
// Next compressed instruction
// ----------------------------