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add fpga-support submodule, exchange srams with inferrable blockrams, remove flat byte enables

Browse source 
switch icache to inferrable blockrams

exchange sram with regfile

switched sram to sram_wrapper in testharness

replace dirty/valid sram with regfile

replace behav_sram with fpga inferrable ram

remove flat byte enables

fix in makefile

add reset to valid regs
This commit is contained in:
Michael Schaffner 2018-08-22 17:45:10 +02:00
parent 5c5e37fc25
commit 4f7bd54065
14 changed files with 230 additions and 189 deletions
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3
.gitmodules vendored
View file

@ -10,3 +10,6 @@
[submodule "src/axi_node"]
path = src/axi_node
url = https://github.com/pulp-platform/axi_node.git
[submodule "src/fpga-support"]
path = src/fpga-support
url = https://github.com/pulp-platform/fpga-support.git

12
Makefile
View file

@ -30,7 +30,8 @@ util := $(wildcard src/util/*.svh) \
src/util/instruction_tracer_if.sv \
src/util/generic_fifo.sv \
src/util/cluster_clock_gating.sv \
src/util/behav_sram.sv
src/util/sram_wrap.sv
# Test packages
test_pkg := $(wildcard tb/test/*/*sequence_pkg.sv*) \
$(wildcard tb/test/*/*_pkg.sv*)
@ -43,7 +44,7 @@ src := $(wildcard src/*.sv) $(wildcard tb/common/*.sv) \
$(wildcard src/axi_slice/*.sv) $(wildcard src/clint/*.sv) \
$(wildcard src/axi_node/*.sv) $(wildcard src/axi_mem_if/src/*.sv) \
$(filter-out src/debug/dm_pkg.sv, $(wildcard src/debug/*.sv)) \
$(wildcard src/debug/debug_rom/*.sv)
$(wildcard src/debug/debug_rom/*.sv) src/fpga-support/rtl/SyncSpRamBeNx64.sv
# look for testbenches
tbs := tb/ariane_tb.sv tb/ariane_testharness.sv
# RISCV asm tests and benchmark setup (used for CI)
@ -156,8 +157,9 @@ verilate_command := $(verilator)
tb/common/pulp_sync.sv \
bootrom/bootrom.sv \
src/util/cluster_clock_gating.sv \
src/util/behav_sram.sv \
src/axi_mem_if/src/axi2mem.sv \
src/util/sram_wrap.sv \
src/fpga-support/rtl/SyncSpRamBeNx64.sv \
src/axi_mem_if/src/axi2mem.sv \
+incdir+src/axi_node \
--unroll-count 256 \
-Werror-PINMISSING \
@ -208,4 +210,4 @@ clean:
rm -f tmp/*.log
.PHONY:
build lint build-moore $(riscv-asm-tests) $(addsuffix _verilator,$(riscv-asm-tests)) check simc sim verilate clean verilate
build lint build-moore $(riscv-asm-tests) $(addsuffix _verilator,$(riscv-asm-tests)) $(riscv-benchmarks) $(addsuffix _verilator,$(riscv-benchmarks)) check simc sim verilate clean verilate

8
include/std_cache_pkg.sv
View file

@ -56,10 +56,10 @@ package std_cache_pkg;
// cache line byte enable
typedef struct packed {
logic [ariane_pkg::DCACHE_TAG_WIDTH-1:0] tag; // byte enable into tag array
logic [ariane_pkg::DCACHE_LINE_WIDTH-1:0] data; // byte enable into data array
logic [DCACHE_DIRTY_WIDTH/2-1:0] dirty; // byte enable into state array
logic [DCACHE_DIRTY_WIDTH/2-1:0] valid; // byte enable into state array
logic [(ariane_pkg::DCACHE_TAG_WIDTH+7)/8-1:0] tag; // byte enable into tag array
logic [(ariane_pkg::DCACHE_LINE_WIDTH+7)/8-1:0] data; // byte enable into data array
logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] dirty; // byte enable into state array
logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] valid; // byte enable into state array
} cl_be_t;
// convert one hot to bin for -> needed for cache replacement

8
src/ariane.sv
View file

@ -141,14 +141,6 @@ module ariane #(
logic [NR_COMMIT_PORTS-1:0][63:0] wdata_commit_id;
logic [NR_COMMIT_PORTS-1:0] we_commit_id;
// --------------
// IF <-> EX
// --------------
logic fetch_req_if_ex;
logic [63:0] fetch_vaddr_if_ex;
logic fetch_valid_ex_if;
logic [63:0] fetch_paddr_ex_if;
exception_t fetch_ex_ex_if;
// --------------
// CSR <-> *
// --------------
logic enable_translation_csr_ex;

8
src/cache_ctrl.sv
View file

@ -287,12 +287,8 @@ module cache_ctrl #(
be_o.valid = hit_way_q;
// set the correct byte enable
for (int unsigned i = 0; i < 8; i++) begin
if (mem_req_q.be[i])
be_o.data[cl_offset + i*8 +: 8] = '1;
end
data_o.data[cl_offset +: 64] = mem_req_q.wdata;
be_o.data[cl_offset>>3 +: 8] = mem_req_q.be;
data_o.data[cl_offset +: 64] = mem_req_q.wdata;
// ~> change the state
data_o.dirty = 1'b1;
data_o.valid = 1'b1;

1
src/fpga-support Submodule

@ -0,0 +1 @@
Subproject commit 3e925e169bd02ebf26e3d4ab65cd1832319cf580

18
src/icache.sv
View file

@ -51,8 +51,8 @@ module icache #(
// signals
logic [ICACHE_SET_ASSOC-1:0] req; // request to memory array
logic [ICACHE_LINE_WIDTH-1:0] data_be; // byte enable for data array
logic [(2**NR_AXI_REFILLS-1):0][63:0] be; // flat byte enable
logic [(ICACHE_LINE_WIDTH+7)/8-1:0] data_be; // byte enable for data array
logic [(2**NR_AXI_REFILLS-1):0][7:0] be; // byte enable
logic [$clog2(ICACHE_NUM_WORD)-1:0] addr; // this is a cache-line address, to memory array
logic we; // write enable to memory array
logic [ICACHE_SET_ASSOC-1:0] hit; // hit from tag compare
@ -77,27 +77,29 @@ module icache #(
// ------------
// Tag RAM
// ------------
sram #(
sram_wrap #(
// tag + valid bit
.DATA_WIDTH ( ICACHE_TAG_WIDTH + 1 ),
.NUM_WORDS ( ICACHE_NUM_WORD )
.DATA_DEPTH ( ICACHE_NUM_WORD )
) tag_sram (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.req_i ( req[i] ),
.we_i ( we ),
.addr_i ( addr ),
.wdata_i ( tag_wdata ),
.be_i ( '1 ),
.be_i ( '1 ),
.rdata_o ( tag_rdata[i] )
);
// ------------
// Data RAM
// ------------
sram #(
.DATA_WIDTH ( ICACHE_LINE_WIDTH ),
.NUM_WORDS ( ICACHE_NUM_WORD )
sram_wrap #(
.DATA_WIDTH ( ICACHE_LINE_WIDTH ),
.DATA_DEPTH ( ICACHE_NUM_WORD )
) data_sram (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.req_i ( req[i] ),
.we_i ( we ),
.addr_i ( addr ),

43
src/nbdcache.sv
View file

@ -76,11 +76,11 @@ module nbdcache #(
// -------------------------------
// Arbiter <-> Datram,
// -------------------------------
logic [DCACHE_SET_ASSOC-1:0] req_ram;
logic [DCACHE_INDEX_WIDTH-1:0] addr_ram;
logic [DCACHE_SET_ASSOC-1:0] req_ram;
logic [DCACHE_INDEX_WIDTH-1:0] addr_ram;
logic we_ram;
cache_line_t wdata_ram;
cache_line_t [DCACHE_SET_ASSOC-1:0] rdata_ram;
cache_line_t [DCACHE_SET_ASSOC-1:0] rdata_ram;
cl_be_t be_ram;
// ------------------
@ -159,11 +159,12 @@ module nbdcache #(
// Memory Arrays
// --------------
for (genvar i = 0; i < DCACHE_SET_ASSOC; i++) begin : sram_block
sram #(
sram_wrap #(
.DATA_WIDTH ( DCACHE_LINE_WIDTH ),
.NUM_WORDS ( DCACHE_NUM_WORDS )
.DATA_DEPTH ( DCACHE_NUM_WORDS )
) data_sram (
.req_i ( req_ram [i] ),
.rst_ni ( rst_ni ),
.we_i ( we_ram ),
.addr_i ( addr_ram[DCACHE_INDEX_WIDTH-1:DCACHE_BYTE_OFFSET] ),
.wdata_i ( wdata_ram.data ),
@ -172,15 +173,16 @@ module nbdcache #(
.*
);
sram #(
sram_wrap #(
.DATA_WIDTH ( DCACHE_TAG_WIDTH ),
.NUM_WORDS ( DCACHE_NUM_WORDS )
.DATA_DEPTH ( DCACHE_NUM_WORDS )
) tag_sram (
.req_i ( req_ram [i] ),
.rst_ni ( rst_ni ),
.we_i ( we_ram ),
.addr_i ( addr_ram[DCACHE_INDEX_WIDTH-1:DCACHE_BYTE_OFFSET] ),
.wdata_i ( wdata_ram.tag ),
.be_i ( be_ram.tag ),
.be_i ( be_ram.tag ),
.rdata_o ( rdata_ram[i].tag ),
.*
);
@ -188,27 +190,28 @@ module nbdcache #(
end
// ----------------
// Dirty SRAM
// Valid/Dirty Regs
// ----------------
logic [DCACHE_DIRTY_WIDTH-1:0] dirty_wdata, dirty_rdata;
for (genvar i = 0; i < DCACHE_SET_ASSOC; i++) begin
assign dirty_wdata[i] = wdata_ram.dirty;
assign dirty_wdata[DCACHE_SET_ASSOC + i] = wdata_ram.valid;
assign dirty_wdata[DCACHE_SET_ASSOC + i] = wdata_ram.valid;
assign rdata_ram[i].valid = dirty_rdata[DCACHE_SET_ASSOC + i];
assign rdata_ram[i].dirty = dirty_rdata[i];
end
sram #(
vdregs #(
.DATA_WIDTH ( DCACHE_DIRTY_WIDTH ),
.NUM_WORDS ( DCACHE_NUM_WORDS )
) dirty_sram (
.DATA_DEPTH ( DCACHE_NUM_WORDS )
) i_vdregs (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.req_i ( |req_ram ),
.we_i ( we_ram ),
.addr_i ( addr_ram[DCACHE_INDEX_WIDTH-1:DCACHE_BYTE_OFFSET] ),
.wdata_i ( dirty_wdata ),
.be_i ( {be_ram.valid, be_ram.dirty} ),
.biten_i ( {be_ram.valid, be_ram.dirty} ),
.rdata_o ( dirty_rdata )
);
@ -265,23 +268,23 @@ module tag_cmp #(
input logic clk_i,
input logic rst_ni,
input logic [NR_PORTS-1:0][DCACHE_SET_ASSOC-1:0] req_i,
input logic [NR_PORTS-1:0][DCACHE_SET_ASSOC-1:0] req_i,
output logic [NR_PORTS-1:0] gnt_o,
input logic [NR_PORTS-1:0][ADDR_WIDTH-1:0] addr_i,
input data_t [NR_PORTS-1:0] wdata_i,
input logic [NR_PORTS-1:0] we_i,
input be_t [NR_PORTS-1:0] be_i,
output data_t [DCACHE_SET_ASSOC-1:0] rdata_o,
input logic [NR_PORTS-1:0][DCACHE_TAG_WIDTH-1:0] tag_i, // tag in - comes one cycle later
output logic [DCACHE_SET_ASSOC-1:0] hit_way_o, // we've got a hit on the corresponding way
output data_t [DCACHE_SET_ASSOC-1:0] rdata_o,
input logic [NR_PORTS-1:0][DCACHE_TAG_WIDTH-1:0] tag_i, // tag in - comes one cycle later
output logic [DCACHE_SET_ASSOC-1:0] hit_way_o, // we've got a hit on the corresponding way
output logic [DCACHE_SET_ASSOC-1:0] req_o,
output logic [DCACHE_SET_ASSOC-1:0] req_o,
output logic [ADDR_WIDTH-1:0] addr_o,
output data_t wdata_o,
output logic we_o,
output be_t be_o,
input data_t [DCACHE_SET_ASSOC-1:0] rdata_i
input data_t [DCACHE_SET_ASSOC-1:0] rdata_i
);
assign rdata_o = rdata_i;

46
src/util/behav_sram.sv
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@ -1,46 +0,0 @@
// Copyright 2017, 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// Date: 13.10.2017
// Description: SRAM Behavioral Model
module sram #(
int unsigned DATA_WIDTH = 64,
int unsigned NUM_WORDS = 1024
)(
input logic clk_i,
input logic req_i,
input logic we_i,
input logic [$clog2(NUM_WORDS)-1:0] addr_i,
input logic [DATA_WIDTH-1:0] wdata_i,
input logic [DATA_WIDTH-1:0] be_i,
output logic [DATA_WIDTH-1:0] rdata_o
);
localparam ADDR_WIDTH = $clog2(NUM_WORDS);
logic [DATA_WIDTH-1:0] ram [NUM_WORDS-1:0];
logic [ADDR_WIDTH-1:0] raddr_q;
// 1. randomize array
// 2. randomize output when no request is active
always_ff @(posedge clk_i) begin
if (req_i) begin
if (!we_i)
raddr_q <= addr_i;
else
for (int i = 0; i < DATA_WIDTH; i++)
if (be_i[i]) ram[addr_i][i] <= wdata_i[i];
end
end
assign rdata_o = ram[raddr_q];
endmodule

56
src/util/regfile.sv Normal file
View file

@ -0,0 +1,56 @@
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>, ETH Zurich
// Michael Schaffner <schaffner@iis.ee.ethz.ch>, ETH Zurich
// Date: 15.08.2018
// Description: SRAM wrapper for FPGA (requires the fpga-support submodule)
//
// Note: the wrapped module contains two different implementations for
// ALTERA and XILINX tools, since these follow different coding styles for
// inferrable RAMS with byte enable. define `FPGA_TARGET_XILINX or
// `FPGA_TARGET_ALTERA in your build environment (default is ALTERA)
module regfile #(
parameter DATA_WIDTH = 64,
parameter DATA_DEPTH = 1024
)(
input logic clk_i,
input logic rst_ni,
input logic we_i,
input logic [$clog2(DATA_DEPTH)-1:0] addr_i,
input logic [DATA_WIDTH-1:0] wdata_i,
input logic [DATA_WIDTH-1:0] biten_i, // bit enable
output logic [DATA_WIDTH-1:0] rdata_o
);
logic [DATA_DEPTH-1:0] regs_d[DATA_WIDTH-1:0];
logic [DATA_DEPTH-1:0] regs_q[DATA_WIDTH-1:0];
genvar k;
generate
for(k=0;k<DATA_DEPTH;k++) begin
for (i;i<DATA_WIDTH;i++) begin
assign regs_d[k][i] = (we_i & biten_i[i]) ? wdata_i[i] : regs_q[k][i];
end
end
endgenerate
assign rdata_o = regs_q[addr_i];
always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
if(~rst_ni) begin
regs_q <= '0;
end else begin
regs_q <= regs_d;
end
end
endmodule : sram_wrap

74
src/util/sram_wrap.sv Normal file
View file

@ -0,0 +1,74 @@
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>, ETH Zurich
// Michael Schaffner <schaffner@iis.ee.ethz.ch>, ETH Zurich
// Date: 15.08.2018
// Description: SRAM wrapper for FPGA (requires the fpga-support submodule)
//
// Note: the wrapped module contains two different implementations for
// ALTERA and XILINX tools, since these follow different coding styles for
// inferrable RAMS with byte enable. define `FPGA_TARGET_XILINX or
// `FPGA_TARGET_ALTERA in your build environment (default is ALTERA)
module sram_wrap #(
parameter DATA_WIDTH = 64,
parameter DATA_DEPTH = 1024,
parameter OUT_REGS = 0 // enables output registers in FPGA macro (read lat = 2)
)(
input logic clk_i,
input logic rst_ni,
input logic req_i,
input logic we_i,
input logic [$clog2(DATA_DEPTH)-1:0] addr_i,
input logic [DATA_WIDTH-1:0] wdata_i,
input logic [(DATA_WIDTH+7)/8-1:0] be_i,
output logic [DATA_WIDTH-1:0] rdata_o
);
localparam DATA_WIDTH_ALIGNED = ((DATA_WIDTH+63)/64)*64;
localparam BE_WIDTH_ALIGNED = (((DATA_WIDTH+7)/8+7)/8)*8;
logic [DATA_WIDTH_ALIGNED-1:0] wdata_aligned;
logic [BE_WIDTH_ALIGNED-1:0] be_aligned;
logic [DATA_WIDTH_ALIGNED-1:0] rdata_aligned;
// align to 64 bits for inferrable macro below
always_comb begin : p_align
wdata_aligned ='0;
be_aligned ='0;
wdata_aligned[DATA_WIDTH-1:0] = wdata_i;
be_aligned[BE_WIDTH_ALIGNED-1:0] = be_i;
rdata_o = rdata_aligned[DATA_WIDTH-1:0];
end
genvar k;
generate
for (k = 0; k<(DATA_WIDTH+63)/64; k++) begin
// unused byte-enable segments (8bits) are culled by the tool
SyncSpRamBeNx64 #(
.ADDR_WIDTH($clog2(DATA_DEPTH)),
.DATA_DEPTH(DATA_DEPTH),
.OUT_REGS (0)
) i_ram (
.Clk_CI ( clk_i ),
.Rst_RBI ( rst_ni ),
.CSel_SI ( req_i ),
.WrEn_SI ( we_i ),
.BEn_SI ( be_aligned[k*8 +: 8] ),
.WrData_DI ( wdata_aligned[k*64 +: 64] ),
.Addr_DI ( addr_i ),
.RdData_DO ( rdata_aligned[k*64 +: 64] )
);
end
endgenerate
endmodule : sram_wrap

83
src/util/xilinx_sram.sv
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@ -1,83 +0,0 @@
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// Author: Florian Zaruba, ETH Zurich
// Date: 13.11.2017
// Description: SRAM Model for Xilinx FPGA
module sram #(
int unsigned DATA_WIDTH = 64,
int unsigned NUM_WORDS = 1024
)(
input logic clk_i,
input logic req_i,
input logic we_i,
input logic [$clog2(NUM_WORDS)-1:0] addr_i,
input logic [DATA_WIDTH-1:0] wdata_i,
input logic [DATA_WIDTH-1:0] be_i,
output logic [DATA_WIDTH-1:0] rdata_o
);
generate
if (NUM_WORDS == 256) begin
// Dirty RAM
if (DATA_WIDTH == 16) begin
localparam NUM_WORDS = 2**8;
logic [NUM_WORDS-1:0][15:0] mem;
always_ff @(posedge clk_i) begin
// write
if (req_i && we_i) begin
for (int unsigned i = 0; i < 16; i++) begin
if (be_i[i])
mem[addr_i][i] <= wdata_i[i];
end
// read
end else if (req_i) begin
rdata_o <= mem[addr_i];
end
end
end
// Data RAM
if (DATA_WIDTH == 44) begin
logic [47:0] data_o;
assign rdata_o = data_o[43:0];
// this is actually 48 bits wide
xilinx_dcache_bank_tag_256x46 TAG_RAM (
.clka ( clk_i ),
.ena ( req_i ),
.wea ( {{be_i[40] & we_i}, {be_i[32] & we_i}, {be_i[24] & we_i}, {be_i[16] & we_i}, {be_i[8] & we_i}, {be_i[0] & we_i}} ),
.addra ( addr_i ),
.dina ( {4'b0, wdata_i} ),
.douta ( data_o )
);
end
// Data RAM
if (DATA_WIDTH == 128) begin
xilinx_dcache_bank_data_256x128 DATA_RAM (
.clka ( clk_i ),
.ena ( req_i ),
.wea ( {{be_i[15] & we_i}, {be_i[14] & we_i}, {be_i[13] & we_i}, {be_i[12] & we_i}, {be_i[11] & we_i}, {be_i[10] & we_i}, {be_i[9] & we_i}, {be_i[8] & we_i}, {be_i[7] & we_i}, {be_i[6] & we_i}, {be_i[5] & we_i}, {be_i[4] & we_i}, {be_i[3] & we_i}, {be_i[2] & we_i}, {be_i[1] & we_i}, {be_i[0] & we_i}}),
.addra ( addr_i ),
.dina ( wdata_i ),
.douta ( rdata_o )
);
end
end
endgenerate
endmodule

45
src/vdregs.sv Normal file
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@ -0,0 +1,45 @@
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>, ETH Zurich
// Michael Schaffner <schaffner@iis.ee.ethz.ch>, ETH Zurich
// Date: 15.08.2018
// Description: valid/dirty regfile for caches
//
module vdregs #(
parameter DATA_WIDTH = 64,
parameter DATA_DEPTH = 1024
)(
input logic clk_i,
input logic rst_ni,
input logic req_i,
input logic we_i,
input logic [$clog2(DATA_DEPTH)-1:0] addr_i,
input logic [DATA_WIDTH-1:0] wdata_i,
input logic [DATA_WIDTH-1:0] biten_i, // bit enable
output logic [DATA_WIDTH-1:0] rdata_o
);
localparam ADDR_WIDTH = $clog2(DATA_DEPTH);
logic [DATA_WIDTH-1:0] regs_q [DATA_DEPTH-1:0];
always_ff @(posedge clk_i or negedge rst_ni) begin
if(~rst_ni) begin
regs_q <= '{default:0};
end else if (req_i) begin
if (we_i) begin
for (int i = 0; i < DATA_WIDTH; i++)
if (biten_i[i]) regs_q[addr_i][i] <= wdata_i[i];
end
rdata_o <= regs_q[addr_i];
end
end
endmodule : vdregs

14
tb/ariane_testharness.sv
View file

@ -233,13 +233,8 @@ module ariane_testharness #(
logic [AXI_DATA_WIDTH/8-1:0] be;
logic [AXI_DATA_WIDTH-1:0] wdata;
logic [AXI_DATA_WIDTH-1:0] rdata;
logic [AXI_DATA_WIDTH-1:0] bit_en;
// convert byte enable to bit enable
for (genvar i = 0; i < AXI_DATA_WIDTH/8; i++) begin
assign bit_en[i*8 +: 8] = {8{be[i]}};
end
axi2mem #(
.AXI_ID_WIDTH ( AXI_ID_WIDTH_SLAVES ),
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
@ -257,16 +252,17 @@ module ariane_testharness #(
.data_i ( rdata )
);
sram #(
sram_wrap #(
.DATA_WIDTH ( AXI_DATA_WIDTH ),
.NUM_WORDS ( NUM_WORDS )
.DATA_DEPTH ( NUM_WORDS )
) i_sram (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.req_i ( req ),
.we_i ( we ),
.addr_i ( addr[$clog2(NUM_WORDS)-1+$clog2(AXI_DATA_WIDTH/8):$clog2(AXI_DATA_WIDTH/8)] ),
.wdata_i ( wdata ),
.be_i ( bit_en ),
.be_i ( be ),
.rdata_o ( rdata )
);