mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-22 05:07:21 -04:00
Add torture test to CI
This commit is contained in:
Michael Schaffner
parent
e9cabc452c
commit
54010e961a
7 changed files with 223 additions and 43 deletions
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@ -23,15 +23,16 @@ variables:
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stages:
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- build
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- test
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- test_std
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# prepare
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build:
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stage: build
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script:
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- ci/build-riscv-tests.sh
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- ci/get-torture.sh
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- make clean
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- make build questa_version=$QUESTASIM_VERSION
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- make verilate verilator=$VERILATOR_ROOT/bin/verilator
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- make torture-gen
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artifacts:
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paths:
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- tmp
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@ -74,4 +75,16 @@ run-benchmarks-verilator:
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dependencies:
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- build
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torture-quest:
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stage: test_std
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script:
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- make torture-rtest
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dependencies:
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- build
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torture-ver:
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stage: test_std
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script:
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- make torture-rtest-verilator
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dependencies:
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- build
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@ -29,6 +29,7 @@ addons:
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- texinfo
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- python-pexpect
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- libusb-1.0-0-dev
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- default-jdk
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env:
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global:
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- RISCV="/home/travis/riscv_install"
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@ -86,5 +87,12 @@ jobs:
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script:
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- ci/build-riscv-tests.sh
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- make -j${NUM_JOBS} run-asm-tests2-verilator verilator=$VERILATOR_ROOT/bin/verilator
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- stage: test
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name: run torture
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script:
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- ci/get-torture.sh
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- make clean
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- make torture-gen
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- make torture-rtest-verilator verilator=$VERILATOR_ROOT/bin/verilator
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# extra time during long builds
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install: travis_wait
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124
Makefile
124
Makefile
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@ -17,14 +17,16 @@ questa_version ?= ${QUESTASIM_VERSION}
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verilator ?= verilator
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# traget option
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target-options ?=
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# additional definess
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defines ?=
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# Sources
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# Package files -> compile first
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ariane_pkg := include/riscv_pkg.sv \
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src/debug/dm_pkg.sv \
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src/axi/src/axi_pkg.sv \
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include/ariane_pkg.sv \
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include/std_cache_pkg.sv \
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include/axi_if.sv
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ariane_pkg := include/riscv_pkg.sv \
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src/debug/dm_pkg.sv \
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src/axi/src/axi_pkg.sv \
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include/ariane_pkg.sv \
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include/std_cache_pkg.sv \
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include/axi_if.sv
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# utility modules
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util := $(wildcard src/util/*.svh) \
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@ -63,11 +65,12 @@ src := $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) \
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# root path
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root-dir := $(shell pwd)
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# look for testbenches
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tbs := tb/ariane_tb.sv tb/ariane_testharness.sv
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# RISCV asm tests and benchmark setup (used for CI)
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# there is a defined test-list with selected CI tests
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# there is a definesd test-list with selected CI tests
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riscv-test-dir := tmp/riscv-tests/build/isa/
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riscv-benchmarks-dir := tmp/riscv-tests/build/benchmarks/
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riscv-asm-tests-list := ci/riscv-asm-tests.list
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@ -76,17 +79,20 @@ riscv-asm-tests := $(shell xargs printf '\n%s' < $(riscv-asm-tests-list)
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riscv-benchmarks := $(shell xargs printf '\n%s' < $(riscv-benchmarks-list) | cut -b 1-)
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# preset which runs a single test
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riscv-test ?= rv64ui-p-add
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# failed test directory
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failed-tests := $(wildcard failedtests/*.S)
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# Search here for include files (e.g.: non-standalone components)
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incdir := ./includes
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# Compile and sim flags
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compile_flag += +cover=bcfst+/dut -incr -64 -nologo -quiet -suppress 13262 -permissive
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compile_flag += +cover=bcfst+/dut -incr -64 -nologo -quiet -suppress 13262 -permissive +define+$(defines)
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uvm-flags += +UVM_NO_RELNOTES
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# Iterate over all include directories and write them with +incdir+ prefixed
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# +incdir+ works for Verilator and QuestaSim
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list_incdir := $(foreach dir, ${incdir}, +incdir+$(dir))
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# RISCV torture setup
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riscv-torture-dir := tmp/riscv-torture/
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riscv-torture-bin := java -Xmx1G -Xss8M -XX:MaxPermSize=128M -jar sbt-launch.jar
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# Build the TB and module using QuestaSim
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build: $(library) $(library)/.build-srcs $(library)/.build-tb $(library)/ariane_dpi.so
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# Optimize top level
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@ -107,10 +113,12 @@ $(library)/.build-tb: $(dpi) $(tbs)
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touch $(library)/.build-tb
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# compile DPIs
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work/%.o: tb/dpi/%.cc $(dpi_hdr)
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$(library)/%.o: tb/dpi/%.cc $(dpi_hdr)
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mkdir -p $(library)
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$(CXX) -shared -fPIC -std=c++0x -Bsymbolic -I$(QUESTASIM_HOME)/include -o $@ $<
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$(library)/ariane_dpi.so: $(dpi)
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mkdir -p $(library)
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# Compile C-code and generate .so file
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$(CXX) -shared -m64 -o $(library)/ariane_dpi.so $? -lfesvr
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@ -118,59 +126,57 @@ $(library):
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# Create the library
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vlib${questa_version} ${library}
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# +jtag_rbb_enable=1
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sim: build $(library)/ariane_dpi.so
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vsim${questa_version} +permissive -64 -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
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+BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
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$(QUESTASIM_FLAGS) \
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-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi -do " do tb/wave/wave_core.do; run -all; exit" \
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vsim${questa_version} +permissive -64 -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
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+BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
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$(QUESTASIM_FLAGS) \
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-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi -do " do tb/wave/wave_core.do; run -all; exit" \
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${top_level}_optimized +permissive-off ++$(riscv-test-dir)/$(riscv-test) ++$(target-options)
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simc: build $(library)/ariane_dpi.so
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vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
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+BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
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$(QUESTASIM_FLAGS) \
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-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi -do " run -all; exit" \
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+BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
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$(QUESTASIM_FLAGS) \
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-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi -do " run -all; exit" \
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${top_level}_optimized +permissive-off ++$(riscv-test-dir)/$(riscv-test) ++$(target-options)
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$(riscv-asm-tests): build $(library)/ariane_dpi.so
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vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
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+BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
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$(QUESTASIM_FLAGS) \
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-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi \
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+BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
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$(QUESTASIM_FLAGS) \
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-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi \
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-do "coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" \
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${top_level}_optimized +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-asm-tests-$@.log
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$(riscv-benchmarks): build $(library)/ariane_dpi.so
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vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
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+BASEDIR=$(riscv-benchmarks-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
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$(QUESTASIM_FLAGS) \
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-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi \
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$(QUESTASIM_FLAGS) \
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-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi \
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-do "coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" \
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${top_level}_optimized +permissive-off ++$(riscv-benchmarks-dir)/$@ ++$(target-options) | tee tmp/riscv-benchmarks-$@.log
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# can use -jX to run ci tests in parallel using X processes
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run-asm-tests: $(riscv-asm-tests)
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make check-asm-tests
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check-asm-tests:
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ci/check-tests.sh tmp/riscv-asm-tests- $(riscv-asm-tests-list)
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ci/check-tests.sh tmp/riscv-asm-tests- $(shell wc -l $(riscv-asm-tests-list) | awk -F " " '{ print $1 }')
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# can use -jX to run ci tests in parallel using X processes
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run-benchmarks: $(riscv-benchmarks)
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make check-benchmarks
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check-benchmarks:
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ci/check-tests.sh tmp/riscv-benchmarks- $(riscv-benchmarks-list)
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ci/check-tests.sh tmp/riscv-benchmarks- $(shell wc -l $(riscv-benchmarks-list) | awk -F " " '{ print $1 }')
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# verilator-specific
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verilate_command := $(verilator) \
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$(ariane_pkg) \
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$(filter-out tb/ariane_bt.sv,$(src)) \
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+define+$(defines) \
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src/util/sram.sv \
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+incdir+src/axi_node \
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+incdir+src/axi_node \
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--unroll-count 256 \
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-Werror-PINMISSING \
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-Werror-IMPLICIT \
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@ -189,7 +195,7 @@ verilate_command := $(verilator)
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--exe tb/ariane_tb.cpp tb/dpi/SimDTM.cc tb/dpi/SimJTAG.cc tb/dpi/remote_bitbang.cc
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# User Verilator, at some point in the future this will be auto-generated
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verilate:
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verilate: $(library)/ariane_dpi.so $(library)/SimJTAG.o $(library)/SimDTM.o $(library)/remote_bitbang.o
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$(verilate_command)
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cd build && make -j${NUM_JOBS} -f Variane_testharness.mk
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@ -209,16 +215,54 @@ $(addsuffix -verilator,$(riscv-benchmarks)): verilate
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run-benchmarks-verilator: $(addsuffix -verilator,$(riscv-benchmarks))
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verify:
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qverify vlog -sv src/csr_regfile.sv
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clean:
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rm -rf work/ *.ucdb
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rm -rf build
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rm -f tmp/*.ucdb
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rm -f tmp/*.log
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rm -f *.wlf *vstf wlft*
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# torture-specific
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torture-gen:
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cd $(riscv-torture-dir) && $(riscv-torture-bin) 'generator/run'
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torture-itest:
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cd $(riscv-torture-dir) && $(riscv-torture-bin) 'testrun/run -a output/test.S'
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torture-rtest: build
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cd $(riscv-torture-dir) && printf "#!/bin/sh\ncd $(root-dir) && make run-torture defines=$(defines)" > call.sh && chmod +x call.sh
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cd $(riscv-torture-dir) && $(riscv-torture-bin) 'testrun/run -r ./call.sh -a output/test.S' | tee output/test.log
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make check-torture
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torture-rtest-verilator: verilate
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cd $(riscv-torture-dir) && printf "#!/bin/sh\ncd $(root-dir) && make run-torture-verilator defines=$(defines)" > call.sh && chmod +x call.sh
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cd $(riscv-torture-dir) && $(riscv-torture-bin) 'testrun/run -r ./call.sh -a output/test.S' | tee output/test-verilator.log
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make check-torture-verilator
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run-torture: build $(library)/ariane_dpi.so
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vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles)+UVM_TESTNAME=${test_case} \
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+BASEDIR=$(riscv-torture-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
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$(QUESTASIM_FLAGS) \
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-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi \
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-do "coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" \
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${top_level}_optimized +permissive-off \
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+signature=$(riscv-torture-dir)/output/test.rtlsim.sig ++$(riscv-torture-dir)/output/test ++$(target-options)
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run-torture-verilator: verilate
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build/Variane_testharness +max-cycles=$(max_cycles) +signature=$(riscv-torture-dir)/output/test.rtlsim.verilator.sig $(riscv-torture-dir)/output/test
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check-torture:
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grep 'All signatures match for output/test' $(riscv-torture-dir)/output/test.log
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diff -s $(riscv-torture-dir)/output/test.spike.sig $(riscv-torture-dir)/output/test.rtlsim.sig
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check-torture-verilator:
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grep 'All signatures match for output/test' $(riscv-torture-dir)/output/test-verilator.log
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diff -s $(riscv-torture-dir)/output/test.spike.sig $(riscv-torture-dir)/output/test.rtlsim.verilator.sig
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clean:
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rm -rf $(riscv-torture-dir)/output/test*
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rm -rf work/ *.ucdb build
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rm -f tmp/*.ucdb tmp/*.log *.wlf *vstf wlft*
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.PHONY:
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build lint build-moore $(riscv-asm-tests) $(addsuffix _verilator,$(riscv-asm-tests)) $(riscv-benchmarks) $(addsuffix _verilator,$(riscv-benchmarks)) check simc sim verilate clean verilate
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build lint build-moore check simc sim verilate clean verilate \
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$(riscv-asm-tests) $(addsuffix _verilator,$(riscv-asm-tests)) \
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$(riscv-benchmarks) $(addsuffix _verilator,$(riscv-benchmarks)) \
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torture-gen torture-igentest torture-rgentest torture-itest torture-rtest
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52
ci/default.config
Normal file
52
ci/default.config
Normal file
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@ -0,0 +1,52 @@
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torture.generator.nseqs 1000
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torture.generator.memsize 1024
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torture.generator.fprnd 0
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torture.generator.amo false
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torture.generator.mul true
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torture.generator.divider true
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torture.generator.segment true
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torture.generator.loop true
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torture.generator.loop_size 64
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torture.generator.mix.xmem 15
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torture.generator.mix.xbranch 25
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torture.generator.mix.xalu 60
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torture.generator.mix.fgen 0
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torture.generator.mix.fpmem 0
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torture.generator.mix.fax 0
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torture.generator.mix.fdiv 0
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torture.generator.mix.vec 0
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torture.generator.vec.vf 1
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torture.generator.vec.seq 20
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torture.generator.vec.memsize 128
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torture.generator.vec.numsregs 64
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torture.generator.vec.mul false
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torture.generator.vec.div false
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torture.generator.vec.mix true
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torture.generator.vec.fpu false
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torture.generator.vec.fma false
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torture.generator.vec.fcvt false
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torture.generator.vec.fdiv false
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torture.generator.vec.amo false
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torture.generator.vec.seg false
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torture.generator.vec.stride false
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torture.generator.vec.pred_alu true
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torture.generator.vec.pred_mem true
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torture.generator.vec.mix.valu 20
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torture.generator.vec.mix.vpop 60
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torture.generator.vec.mix.vmem 20
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torture.generator.vec.mix.vonly 0
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torture.testrun.maxcycles 10000000
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torture.testrun.virtual false
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torture.testrun.seek true
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torture.testrun.dump false
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torture.testrun.vec false
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torture.overnight.errors 1
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torture.overnight.minutes 1
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torture.overnight.outdir output/failedtests
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torture.overnight.email your@email.address
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21
ci/get-torture.sh
Executable file
21
ci/get-torture.sh
Executable file
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@ -0,0 +1,21 @@
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#!/bin/bash
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set -e
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ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)
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VERSION="59b0f0f224ff4f1eb6ebb1b4dd7eaf1ab3fac2e5"
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cd $ROOT/tmp
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if [ -z ${NUM_JOBS} ]; then
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NUM_JOBS=1
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fi
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[ -d $ROOT/tmp/riscv-torture ] || git clone https://github.com/ucb-bar/riscv-torture.git
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cd riscv-torture
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git checkout $VERSION
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git submodule update --init --recursive
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# copy ariane specific config
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cp config/default.config config/default.config.bak
|
||||
cp $ROOT/ci/default.config config/default.config
|
||||
git apply $ROOT/ci/torture_make.patch
|
||||
|
||||
41
ci/torture_make.patch
Normal file
41
ci/torture_make.patch
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
diff --git a/output/Makefile b/output/Makefile
|
||||
index cf1214f..c81bccc 100644
|
||||
--- a/output/Makefile
|
||||
+++ b/output/Makefile
|
||||
@@ -20,9 +20,9 @@ extra_files =
|
||||
#--------------------------------------------------------------------
|
||||
|
||||
RISCV_GCC = riscv64-unknown-elf-gcc
|
||||
-RISCV_GCC_OPTS = -nostdlib -nostartfiles -Wa,-march=RVIMAFDXhwacha
|
||||
+RISCV_GCC_OPTS = -nostdlib -nostartfiles -Wa,-march=rv64imc
|
||||
RISCV_OBJDUMP = riscv64-unknown-elf-objdump --disassemble-all --section=.text --section=.data --section=.bss
|
||||
-RISCV_SIM = spike --extension=hwacha
|
||||
+RISCV_SIM = spike
|
||||
|
||||
#------------------------------------------------------------
|
||||
# Build assembly tests
|
||||
@@ -38,9 +38,6 @@ $(asm_tests_dump): %.dump: %
|
||||
$(asm_tests_bin): %: %.S $(extra_files)
|
||||
$(RISCV_GCC) $(RISCV_GCC_OPTS) -I../env/p -T../env/p/link.ld $< -o $@
|
||||
|
||||
-$(asm_tests_hex): %.hex: % $(extra_files)
|
||||
- elf2hex 16 16384 $< > $@
|
||||
-
|
||||
$(asm_tests_sig): %.sig: %
|
||||
$(RISCV_SIM) +signature=$@ $<
|
||||
|
||||
@@ -51,12 +48,12 @@ run: $(asm_tests_sig)
|
||||
echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' \
|
||||
$(asm_tests_sig); echo;
|
||||
|
||||
-junk += $(asm_tests_bin) $(asm_tests_dump) $(asm_tests_sig) $(asm_tests_hex)
|
||||
+junk += $(asm_tests_bin) $(asm_tests_dump) $(asm_tests_sig)
|
||||
|
||||
#------------------------------------------------------------
|
||||
# Default
|
||||
|
||||
-all: $(asm_tests_dump) $(asm_tests_hex)
|
||||
+all: $(asm_tests_dump)
|
||||
|
||||
#------------------------------------------------------------
|
||||
# Clean up
|
||||
|
|
@ -38,3 +38,4 @@ make clean
|
|||
make -j${NUM_JOBS} verilate verilator=$VERILATOR_ROOT/bin/verilator
|
||||
make -j${NUM_JOBS} run-asm-tests-verilator verilator=$VERILATOR_ROOT/bin/verilator
|
||||
make -j${NUM_JOBS} run-benchmarks-verilator verilator=$VERILATOR_ROOT/bin/verilator
|
||||
make -j${NUM_JOBS} run-torture-verilator verilator=$VERILATOR_ROOT/bin/verilator
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue