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✨ Add debug hart ctrl memory interface

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This commit is contained in:
Florian Zaruba 2018-07-11 16:25:27 -07:00
parent 82c06d0292
commit 54bbced94f
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GPG key ID: E742FFE8EC38A792
10 changed files with 206 additions and 44 deletions
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39
Makefile
View file

@ -172,20 +172,33 @@ $(tests): build
-do "coverage save -onexit $@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" \
${library}.$@_tb_optimized
# User Verilator
# User Verilator, at some point in the future this will be auto-generated
verilate:
$(verilator) $(ariane_pkg) $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) $(wildcard src/axi_slice/*.sv) \
$(filter-out src/debug/dm_pkg.sv, $(wildcard src/debug/*.sv)) src/util/generic_fifo.sv tb/common/SimDTM.v bootrom/bootrom.sv \
src/util/cluster_clock_gating.sv src/util/behav_sram.sv src/axi_mem_if/src/axi2mem.sv tb/agents/axi_if/axi_if.sv \
+incdir+src/axi_node --vpi --trace-structs \
--unroll-count 256 -Werror-PINMISSING -Werror-IMPLICIT -LDFLAGS "-lfesvr" -CFLAGS "-std=c++11" -Wall --cc --trace \
-Wno-fatal \
-Wno-PINCONNECTEMPTY \
-Wno-DECLFILENAME \
-Wno-UNOPTFLAT \
-Wno-UNUSED \
-Wno-ASSIGNDLY \
$(list_incdir) --top-module ariane_wrapped --exe tb/ariane_tb.cpp tb/dpi/SimDTM.cc
$(verilator) \
$(ariane_pkg) \
$(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) \
$(wildcard src/axi_slice/*.sv) \
$(filter-out src/debug/dm_pkg.sv, $(wildcard src/debug/*.sv)) \
src/debug/debug_rom/debug_rom.sv \
src/util/generic_fifo.sv \
tb/common/SimDTM.v \
bootrom/bootrom.sv \
src/util/cluster_clock_gating.sv \
src/util/behav_sram.sv \
src/axi_mem_if/src/axi2mem.sv \
tb/agents/axi_if/axi_if.sv \
+incdir+src/axi_node \
--unroll-count 256 \
-Werror-PINMISSING \
-Werror-IMPLICIT \
-Wno-fatal \
-Wno-PINCONNECTEMPTY \
-Wno-DECLFILENAME \
-Wno-UNOPTFLAT \
-Wno-UNUSED \
-Wno-ASSIGNDLY \
-LDFLAGS "-lfesvr" -CFLAGS "-std=c++11" -Wall --cc --trace --vpi --trace-structs \
$(list_incdir) --top-module ariane_wrapped --exe tb/ariane_tb.cpp tb/dpi/SimDTM.cc
cd obj_dir && make -j8 -f Variane_wrapped.mk
# -Werror-UNDRIVEN

2
README.md
View file

@ -11,7 +11,7 @@ It has configurable size, separate TLBs, a hardware PTW and branch-prediction (b
## Getting Started
Go and get the [RISC-V tools](https://github.com/riscv/riscv-tools).
Go and get the [RISC-V tools](https://github.com/riscv/riscv-tools). Make sure that your `RISCV` environment variable points to your RISC-V installation.
Checkout the repository and initialize all submodules
```

2
src/ariane.sv
View file

@ -626,7 +626,7 @@ module ariane #(
$fwrite(f, "%d 0x%0h (0x%h) DASM(%h)\n", cycles, commit_instr_id_commit[i].pc, commit_instr_id_commit[i].ex.tval[31:0], commit_instr_id_commit[i].ex.tval[31:0]);
end else if (commit_ack[i] && commit_instr_id_commit[i].ex.valid) begin
if (commit_instr_id_commit[i].ex.cause == 2) begin
$fwrite(f, "Exception Cause: Illegal Instructions, DASM(%h)\n", commit_instr_id_commit[i].ex.tval[31:0]);
$fwrite(f, "Exception Cause: Illegal Instructions, DASM(%h) PC=%h\n", commit_instr_id_commit[i].ex.tval[31:0], commit_instr_id_commit[i].pc);
end else begin
$fwrite(f, "Exception Cause: %5d\n", commit_instr_id_commit[i].ex.cause);
end

10
src/ariane_wrapped.sv
View file

@ -86,14 +86,18 @@ module ariane_wrapped #(
);
// debug module
dm_top #(
.NrHarts ( 1 ) // current implementation only supports 1 hart
.NrHarts ( 1 ), // current implementation only supports 1 hart
.AxiIdWidth ( AXI_ID_WIDTH_SLAVES ),
.AxiAddrWidth ( AXI_ADDRESS_WIDTH ),
.AxiDataWidth ( AXI_DATA_WIDTH ),
.AxiUserWidth ( AXI_USER_WIDTH )
) i_dm_top (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ), // PoR
.ndmreset_o ( ndmreset ),
.dmactive_o ( ), // active debug session
.debug_req_o ( debug_req ),
.axi_slave ( master[0] ),
.axi_slave ( master[2] ),
.dmi_rst_ni ( rst_ni ),
.dmi_req_valid_i ( debug_req_valid ),
.dmi_req_ready_o ( debug_req_ready ),
@ -161,7 +165,7 @@ module ariane_wrapped #(
) i_axi2mem (
.clk_i ( clk_i ),
.rst_ni ( ndmreset_n ),
.slave ( master[2] ),
.slave ( master[0] ),
.req_o ( req ),
.we_o ( we ),
.addr_o ( addr ),

2
src/debug/debug_rom/Makefile
View file

@ -8,7 +8,7 @@ OBJCOPY=riscv64-unknown-elf-objcopy
all: $(debug_rom)
%.img: %.bin
dd if=$< of=$@ bs=128 count=2
dd if=$< of=$@ bs=128 count=1
%.bin: %.elf
$(OBJCOPY) -O binary $< $@

9
src/debug/dm_csrs.sv
View file

@ -50,7 +50,8 @@ module dm_csrs #(
input logic [NrHarts-1:0] set_cmderror_i, // an error occured
input dm::cmderr_t [NrHarts-1:0] cmderror_i, // this error occured
input logic [NrHarts-1:0] cmdbusy_i, // cmd is currently busy executing
output [dm::ProgBufSize-1:0][31:0] progbuf_o // to system bus
output logic [dm::ProgBufSize-1:0][31:0] progbuf_o, // to system bus
output logic [dm::DataCount-1:0][31:0] data_o // optional data register (to system bus)
);
// the amount of bits we need to represent all harts
localparam HartSelLen = (NrHarts == 1) ? 1 : $clog2(NrHarts);
@ -136,6 +137,7 @@ module dm_csrs #(
cmderr_d = cmderr_q;
command_d = command_q;
progbuf_d = progbuf_q;
data_d = data_q;
resp_queue_data = 32'0;
command_write_o = 1'b0;
@ -231,7 +233,8 @@ module dm_csrs #(
// if the PoR is set we want to re-set the other system as well
assign ndmreset_o = dmcontrol_q.ndmreset | (~rst_ni);
assign command_o = command_q;
assign progbuf_o = progbuf_q;
assign data_o = data_q;
// response FIFO
fifo #(
.dtype ( logic [31:0] ),
@ -273,11 +276,13 @@ module dm_csrs #(
cmderr_q <= dm::CmdErrNone;
command_q <= '0;
progbuf_q <= '0;
data_q <= '0;
end else begin
dmcontrol_q <= dmcontrol_d;
cmderr_q <= cmderr_d;
command_q <= command_q;
progbuf_q <= progbuf_d;
data_q <= data_d;
end
end
end

10
src/debug/dm_ctrl.sv
View file

@ -8,7 +8,7 @@
* CONDITIONS OF ANY KIND, either express or implied. See the License for the
* specific language governing permissions and limitations under the License.
*
* File: axi_riscv_debug_module.sv
* File: dm_ctrl.sv
* Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
* Date: 1.7.2018
*
@ -37,8 +37,8 @@ module dm_ctrl (
output logic set_cmderror_o,
output dm::cmderr_t cmderror_o,
output logic cmdbusy_o,
// from AXI module
input logic ackhalt_i // hart acknowledged halt request
// from hart communication module
input logic halted_i // hart is halted
);
logic havereset_d, havereset_q;
@ -66,13 +66,15 @@ module dm_ctrl (
kRunning: begin
if (haltreq_i) state_d = kHaltReq;
// the core is already halted
if (halted_i) state_d = kHalted;
end
kHaltReq: begin
// request entering debug mode
debug_req_o = 1'b1;
// hart acknowledged ~> halt
if (ackhalt_i) state_d = kHalted;
if (halted_i) state_d = kHalted;
end
kHalted: begin

91
src/debug/dm_mem.sv Normal file
View file

@ -0,0 +1,91 @@
/* Copyright 2018 ETH Zurich and University of Bologna.
* Copyright and related rights are licensed under the Solderpad Hardware
* License, Version 0.51 (the “License”); you may not use this file except in
* compliance with the License. You may obtain a copy of the License at
* http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
* or agreed to in writing, software, hardware and materials distributed under
* this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
* CONDITIONS OF ANY KIND, either express or implied. See the License for the
* specific language governing permissions and limitations under the License.
*
* File: dm_mem.sv
* Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
* Date: 11.7.2018
*
* Description: Memory module for execution-based debug clients
*
*/
module dm_mem #(
parameter int NrHarts = -1
)(
input logic clk_i, // Clock
input logic dmactive_i, // debug module reset
output logic [NrHarts-1:0] halted_o, // hart acknowledge halt
output logic [NrHarts-1:0] going_o, // hart is running
output logic [NrHarts-1:0] resuming_o, // hart is resuming
output logic [NrHarts-1:0] exception_o, // hart ran into an exception
input logic [dm::ProgBufSize-1:0][31:0] progbuf_i, // program buffer to expose
input logic [dm::DataCount-1:0][31:0] data_i, // data in
// SRAM interface
input logic req_i,
input logic we_i,
input logic [63:0] addr_i,
input logic [63:0] wdata_i,
input logic [7:0] be_i,
output logic [63:0] rdata_o
);
localparam HartSelLen = (NrHarts == 1) ? 1 : $clog2(NrHarts);
logic [63:0] rom_rdata;
// distinguish whether we need to forward data from the ROM or the FSM
// latch the address for this
logic fwd_rom_d, fwd_rom_q;
debug_rom i_debug_rom (
.clk_i,
.req_i,
.addr_i,
.rdata_o (rom_rdata)
);
logic [HartSelLen-1:0] hart_sel;
assign hart_sel = wdata_i[HartSelLen-1:0];
// read/write logic
always_comb begin
halted_o = '0;
going_o = '0;
resuming_o = '0;
exception_o = '0;
rdata_o = fwd_rom_q ? rom_rdata : '0;
// we've got a new request
if (req_i) begin
// this is a write
if (we_i) begin
case (addr_i[dm::DbgAddressBits-1:0])
dm::Halted: halted_o[hart_sel] = 1'b1;
dm::Going: going_o[hart_sel] = 1'b1;
dm::Resuming: resuming_o[hart_sel] = 1'b1;
dm::Exception: exception_o[hart_sel] = 1'b1;
endcase
// this is a read
end else begin
end
end
end
// ROM starts at the HaltAddress of the core e.g.: it immediately jumps to
// the ROM base address
assign fwd_rom_d = (addr_i[dm::DbgAddressBits-1:0] >= dm::HaltAddress) ? 1'b1 : 1'b0;
always_ff @(posedge clk_i) begin
if (~dmactive_i) begin
fwd_rom_q <= 1'b0;
end else begin
fwd_rom_q <= fwd_rom_d;
end
end
endmodule

18
src/debug/dm_pkg.sv
View file

@ -8,7 +8,7 @@
* CONDITIONS OF ANY KIND, either express or implied. See the License for the
* specific language governing permissions and limitations under the License.
*
* File: axi_riscv_debug_module.sv
* File: dm_pkg.sv
* Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
* Date: 30.6.2018
*
@ -23,10 +23,16 @@ package dm;
// amount of data count registers implemented
parameter logic [3:0] DataCount = 5'h0;
// #define HALTED 0x100
// #define GOING 0x104
// #define RESUMING 0x108
// #define EXCEPTION 0x10C
// address to which a hart should jump when it was requested to halt
parameter logic [63:0] HaltAddress = 64'h800;
parameter DbgAddressBits = 12;
parameter logic [DbgAddressBits-1:0] Halted = 'h100;
parameter logic [DbgAddressBits-1:0] Going = 'h104;
parameter logic [DbgAddressBits-1:0] Resuming = 'h108;
parameter logic [DbgAddressBits-1:0] Exception = 'h10C;
// #define FLAGS 0x400
// #define FLAG_GO 0
// #define FLAG_RESUME 1
@ -66,8 +72,6 @@ package dm;
HaltSum0 = 8'h40
} dm_csr_t;
// address to which a hart should jump when it was requested to halt
localparam logic [63:0] HaltAddress = 64'h1000;
// debug causes
localparam logic [2:0] CauseBreakpoint = 3'h1;
localparam logic [2:0] CauseTrigger = 3'h2;

67
src/debug/dm_top.sv
View file

@ -8,7 +8,7 @@
* CONDITIONS OF ANY KIND, either express or implied. See the License for the
* specific language governing permissions and limitations under the License.
*
* File: axi_riscv_debug_module.sv
* File: dm_top.sv
* Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
* Date: 30.6.2018
*
@ -18,14 +18,19 @@
*/
module dm_top #(
parameter int NrHarts = -1
parameter int NrHarts = -1,
parameter int AxiIdWidth = -1,
parameter int AxiAddrWidth = -1,
parameter int AxiDataWidth = -1,
parameter int AxiUserWidth = -1
)(
input logic clk_i, // clock
input logic rst_ni, // asynchronous reset active low, connect PoR here, not the system reset
output logic ndmreset_o, // non-debug module reset
output logic dmactive_o, // debug module is active
output logic [NrHarts-1:0] debug_req_o, // async debug request
AXI_BUS.Slave axi_slave, // bus slave
AXI_BUS.Slave axi_slave, // bus slave, for an execution based technique
// Connection to DTM - compatible to RocketChip Debug Module
input logic dmi_rst_ni,
input logic dmi_req_valid_i,
@ -56,6 +61,7 @@ module dm_top #(
dm::cmderr_t [NrHarts-1:0] cmderror;
logic [NrHarts-1:0] cmdbusy;
logic [dm::ProgBufSize-1:0][31:0] progbuf;
logic [dm::DataCount-1:0][31:0] data;
dm_csrs #(
.NrHarts(NrHarts)
@ -88,7 +94,8 @@ module dm_top #(
.set_cmderror_i ( set_cmderror ),
.cmderror_i ( cmderror ),
.cmdbusy_i ( cmdbusy ),
.progbuf_o ( progbuf )
.progbuf_o ( progbuf ),
.data_o ( data )
);
logic [NrHarts-1:0] ackhalt;
@ -115,15 +122,51 @@ module dm_top #(
.set_cmderror_o ( set_cmderror [i] ),
.cmderror_o ( cmderror [i] ),
.cmdbusy_o ( cmdbusy [i] ),
.ackhalt_i ( ackhalt [i] )
.halted_i ( ackhalt [i] )
);
end
// Debug AXI Bus
assign ackhalt = '0;
assign axi_slave.aw_ready = 1'b1;
assign axi_slave.ar_ready = 1'b1;
assign axi_slave.w_ready = 1'b1;
assign axi_slave.r_valid = 1'b0;
assign axi_slave.b_valid = 1'b0;
logic req;
logic we;
logic [63:0] addr;
logic [7:0] be;
logic [63:0] wdata;
logic [63:0] rdata;
logic [63:0] bit_en;
dm_mem #(
.NrHarts (NrHarts)
) i_dm_mem (
.clk_i ( clk_i ),
.dmactive_i ( dmactive_o),
.halted_o ( ackhalt ),
.going_o ( ),
.resuming_o ( ),
.exception_o ( ),
.progbuf_i ( progbuf ), // program buffer to expose
.data_i ( data ), // data in
.req_i ( req ),
.we_i ( we ),
.addr_i ( addr ),
.wdata_i ( wdata ),
.be_i ( be ),
.rdata_o ( rdata )
);
axi2mem #(
.AXI_ID_WIDTH ( AxiIdWidth ),
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
.AXI_USER_WIDTH ( AxiUserWidth )
) i_axi2mem (
.clk_i ( clk_i ),
.rst_ni ( dmactive_o ),
.slave ( axi_slave ),
.req_o ( req ),
.we_o ( we ),
.addr_o ( addr ),
.be_o ( be ),
.data_o ( wdata ),
.data_i ( rdata )
);
endmodule