mirror of
https://github.com/openhwgroup/cva6.git
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✨ Add debug ROM
This commit is contained in:
Florian Zaruba
parent
d848f7f2fd
commit
82c06d0292
9 changed files with 174 additions and 288 deletions
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@ -1,4 +1,4 @@
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bootrom_img = bootrom.img bootrom.elf
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bootrom_img = bootrom.img
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GCC=riscv64-unknown-elf-gcc
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OBJCOPY=riscv64-unknown-elf-objcopy
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@ -8,22 +8,18 @@
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* CONDITIONS OF ANY KIND, either express or implied. See the License for the
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* specific language governing permissions and limitations under the License.
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*
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* File: bootrom.v
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* Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
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* Date: 10.7.2018
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* File: $filename.v
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*
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* Description: First-stage Boot-loader
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* Description: Auto-generated bootrom
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*/
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// TODO(zarubaf) Auto-generate this!
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module bootrom (
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input logic clk_i,
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input logic req_i,
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input logic [63:0] addr_i,
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output logic [63:0] rdata_o
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);
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localparam int RomSize = 32;
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localparam int RomSize = 16;
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const logic [RomSize-1:0][63:0] mem = {
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64'h00000000_00000000,
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98
bootrom/gen_rom.py
Normal file → Executable file
98
bootrom/gen_rom.py
Normal file → Executable file
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@ -1,6 +1,25 @@
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#!/usr/bin/env python3
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license = """
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from string import Template
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import argparse
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import os.path
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import sys
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parser = argparse.ArgumentParser(description='Convert binary file to verilog rom')
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parser.add_argument('filename', metavar='filename', nargs=1,
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help='filename of input binary')
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args = parser.parse_args()
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file = args.filename[0];
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# check that file exists
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if not os.path.isfile(file):
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print("File {} does not exist.".format(filename))
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sys.exit(1)
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filename = os.path.splitext(file)[0]
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license = """\
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/* Copyright 2018 ETH Zurich and University of Bologna.
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* Copyright and related rights are licensed under the Solderpad Hardware
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* License, Version 0.51 (the “License”); you may not use this file except in
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@ -11,8 +30,83 @@ license = """
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* CONDITIONS OF ANY KIND, either express or implied. See the License for the
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* specific language governing permissions and limitations under the License.
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*
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* File: bootrom.v
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* File: $filename.v
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*
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* Description: Auto-generated bootrom
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*/
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// Auto-generated code
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"""
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module = """\
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module $filename (
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input logic clk_i,
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input logic req_i,
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input logic [63:0] addr_i,
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output logic [63:0] rdata_o
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);
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localparam int RomSize = $size;
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const logic [RomSize-1:0][63:0] mem = {
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$content
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};
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logic [$$clog2(RomSize)-1:0] addr_q;
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always_ff @(posedge clk_i) begin
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if (req_i) begin
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addr_q = addr_i[$$clog2(RomSize)-1+3:3];
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end
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end
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assign rdata_o = mem[addr_q];
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endmodule
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"""
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rom = []
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with open(filename + ".img", "rb") as f:
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byte = True;
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while byte:
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word = ""
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# read 64-bit a.k.a 8 byte
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for i in range(0, 8):
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byte = f.read(1)
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if i == 4:
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word = "_" + word
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if byte:
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word = byte.hex() + word
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# fill up with zeros if unaligned
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else:
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pass
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# word += "00";
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if word != "_":
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word = "64'h" + word
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# print(word)
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rom.append(word)
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f.close()
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rom.reverse()
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# open file for writing
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with open(filename + ".sv", "w") as f:
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# some string preparations
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rom_str = ""
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i = 0
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for r in rom:
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i += 1
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rom_str += r + ",\n ";
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rom_str.rstrip()
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# strip the last whitespace
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rom_str = rom_str[:-10]
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# write files
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f.write(license)
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s = Template(module)
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f.write(s.substitute(filename=filename, size=i, content=rom_str))
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f.close()
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3
src/debug/debug_rom/.gitignore
vendored
Normal file
3
src/debug/debug_rom/.gitignore
vendored
Normal file
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*.bin
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*.elf
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debug_rom.img
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@ -1,31 +1,21 @@
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# See LICENSE.SiFive for license details
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# Recursive make is bad, but in this case we're cross compiling which is a
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# pretty unusual use case.
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CC = $(RISCV)/bin/riscv64-unknown-elf-gcc
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OBJCOPY = $(RISCV)/bin/riscv64-unknown-elf-objcopy
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debug_rom = debug_rom.img
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COMPILE = $(CC) -nostdlib -nostartfiles -I$(RISCV)/include/ -Tlink.ld
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GCC=riscv64-unknown-elf-gcc
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OBJCOPY=riscv64-unknown-elf-objcopy
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ELFS = debug_rom
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DEPS = debug_rom.S link.ld
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all: $(debug_rom)
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all: $(patsubst %,%.h,$(ELFS))
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%.img: %.bin
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dd if=$< of=$@ bs=128 count=2
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publish: debug_rom.scala
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mv $< ../../src/main/scala/uncore/devices/debug/DebugRomContents.scala
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%.bin: %.elf
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$(OBJCOPY) -O binary $< $@
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%.scala: %.raw
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xxd -i $^ | sed -e "s/^unsigned char debug_rom_raw\[\] = {/\/\/ This file was auto-generated by 'make publish' in debug\/ directory.\n\npackage uncore.devices\n\nobject DebugRomContents {\n\n def apply() : Array[Byte] = { Array (/" \
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-e "s/};/ ).map(_.toByte) }\n\n}/" \
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-e "s/^unsigned int debug_rom_raw_len.*//" > $@
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%.raw: %
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$(OBJCOPY) -O binary --only-section .text $^ $@
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debug_rom: $(DEPS)
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$(COMPILE) -o $@ $^
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%.elf: %.S link.ld
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$(GCC) -I$(RISCV)/include -Tlink.ld $< -nostdlib -static -Wl,--no-gc-sections -o $@
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clean:
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rm -f $(ELFS) debug_rom*.raw debug_rom*.h
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rm $(debug_rom)
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49
src/debug/debug_rom/debug_rom.sv
Normal file
49
src/debug/debug_rom/debug_rom.sv
Normal file
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@ -0,0 +1,49 @@
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/* Copyright 2018 ETH Zurich and University of Bologna.
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* Copyright and related rights are licensed under the Solderpad Hardware
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* License, Version 0.51 (the “License”); you may not use this file except in
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* compliance with the License. You may obtain a copy of the License at
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* http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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* or agreed to in writing, software, hardware and materials distributed under
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* this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
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* CONDITIONS OF ANY KIND, either express or implied. See the License for the
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* specific language governing permissions and limitations under the License.
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*
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* File: $filename.v
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*
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* Description: Auto-generated bootrom
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*/
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// Auto-generated code
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module debug_rom (
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input logic clk_i,
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input logic req_i,
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input logic [63:0] addr_i,
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output logic [63:0] rdata_o
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);
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localparam int RomSize = 12;
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const logic [RomSize-1:0][63:0] mem = {
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64'h7b200073_7b202473,
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64'h10802423_f1402473,
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64'h30000067_10002223,
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64'h7b202473_00100073,
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64'h10002623_fddff06f,
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64'hfc0418e3_00247413,
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64'h40044403_f1402473,
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64'h02041063_00147413,
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64'h40044403_10802023,
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64'hf1402473_7b241073,
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64'h0ff0000f_0340006f,
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64'h04c0006f_00c0006f
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};
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logic [$clog2(RomSize)-1:0] addr_q;
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always_ff @(posedge clk_i) begin
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if (req_i) begin
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addr_q = addr_i[$clog2(RomSize)-1+3:3];
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end
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end
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assign rdata_o = mem[addr_q];
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endmodule
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1
src/debug/debug_rom/gen_rom.py
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1
src/debug/debug_rom/gen_rom.py
Symbolic link
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@ -0,0 +1 @@
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../../../bootrom/gen_rom.py
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@ -22,6 +22,15 @@ package dm;
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parameter logic [4:0] ProgBufSize = 5'h4;
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// amount of data count registers implemented
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parameter logic [3:0] DataCount = 5'h0;
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// #define HALTED 0x100
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// #define GOING 0x104
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// #define RESUMING 0x108
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// #define EXCEPTION 0x10C
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// #define FLAGS 0x400
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// #define FLAG_GO 0
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// #define FLAG_RESUME 1
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// debug registers
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typedef enum logic [7:0] {
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Data0 = 8'h04,
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