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Add support for Nexys Video board (#1925)

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Saute0212 2024-04-04 18:13:32 +09:00 • committed by GitHub
parent 5c7ddcbcc5
commit 5920e3d125
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19 changed files with 504 additions and 5764 deletions
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24
Makefile
View file

@ -36,8 +36,9 @@ test-location ?= output/test
torture-logs :=
# custom elf bin to run with sim or sim-verilator
elf_file ?= tmp/riscv-tests/build/benchmarks/dhrystone.riscv
# board name for bitstream generation. Currently supported: kc705, genesys2
# board name for bitstream generation. Currently supported: kc705, genesys2, nexys_video
BOARD ?= genesys2
# root path
mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST)))
root-dir := $(dir $(mkfile_path))
@ -76,6 +77,10 @@ else ifeq ($(BOARD), vc707)
XILINX_PART := xc7vx485tffg1761-2
XILINX_BOARD := xilinx.com:vc707:part0:1.3
CLK_PERIOD_NS := 20
else ifeq ($(BOARD), nexys_video)
XILINX_PART := xc7a200tsbg484-1
XILINX_BOARD := digilentinc.com:nexys_video:part0:1.1
CLK_PERIOD_NS := 40
else
$(error Unknown board - please specify a supported FPGA board)
endif
@ -92,6 +97,11 @@ endif
# cv64a6_imafdc_sv39, cv32a6_imac_sv0, cv32a6_imac_sv32, cv32a6_imafc_sv32, cv32a6_ima_sv32_fpga
# Changing the default target to cv32a60x for Step1 verification
target ?= cv64a6_imafdc_sv39
ifeq ($(target), cv64a6_imafdc_sv39)
XLEN ?= 64
else
XLEN ?= 32
endif
ifndef TARGET_CFG
export TARGET_CFG = $(target)
endif
@ -214,8 +224,8 @@ copro_src := $(addprefix $(root-dir), $(copro_src))
uart_src := $(wildcard corev_apu/fpga/src/apb_uart/src/*.vhd)
uart_src := $(addprefix $(root-dir), $(uart_src))
fpga_src := $(wildcard corev_apu/fpga/src/*.sv) $(wildcard corev_apu/fpga/src/bootrom/*.sv) $(wildcard corev_apu/fpga/src/ariane-ethernet/*.sv) common/local/util/tc_sram_fpga_wrapper.sv vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx64.sv
fpga_src := $(addprefix $(root-dir), $(fpga_src))
fpga_src := $(wildcard corev_apu/fpga/src/*.sv) $(wildcard corev_apu/fpga/src/ariane-ethernet/*.sv) common/local/util/tc_sram_fpga_wrapper.sv vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx64.sv
fpga_src := $(addprefix $(root-dir), $(fpga_src)) src/bootrom/bootrom_$(XLEN).sv
# look for testbenches
tbs := corev_apu/tb/ariane_tb.sv corev_apu/tb/ariane_testharness.sv core/cva6_rvfi.sv
@ -694,6 +704,9 @@ fpga_filter += $(addprefix $(root-dir), common/local/util/instr_tracer.sv)
fpga_filter += $(addprefix $(root-dir), vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv)
fpga_filter += $(addprefix $(root-dir), common/local/util/tc_sram_wrapper.sv)
src/bootrom/bootrom_$(XLEN).sv:
$(MAKE) -C corev_apu/fpga/src/bootrom BOARD=$(BOARD) XLEN=$(XLEN) bootrom_$(XLEN).sv
fpga: $(ariane_pkg) $(src) $(fpga_src) $(uart_src) $(src_flist)
@echo "[FPGA] Generate sources"
@echo read_vhdl {$(uart_src)} > corev_apu/fpga/scripts/add_sources.tcl
@ -702,7 +715,7 @@ fpga: $(ariane_pkg) $(src) $(fpga_src) $(uart_src) $(src_flist)
@echo read_verilog -sv {$(filter-out $(fpga_filter), $(src))} >> corev_apu/fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(fpga_src)} >> corev_apu/fpga/scripts/add_sources.tcl
@echo "[FPGA] Generate Bitstream"
cd corev_apu/fpga && make BOARD=$(BOARD) XILINX_PART=$(XILINX_PART) XILINX_BOARD=$(XILINX_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS)
$(MAKE) -C corev_apu/fpga BOARD=$(BOARD) XILINX_PART=$(XILINX_PART) XILINX_BOARD=$(XILINX_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS)
.PHONY: fpga
@ -713,7 +726,8 @@ clean:
rm -rf $(riscv-torture-dir)/output/test*
rm -rf $(library)/ $(dpi-library)/ $(ver-library)/ $(vcs-library)/
rm -f tmp/*.ucdb tmp/*.log *.wlf *vstf wlft* *.ucdb
cd corev_apu/fpga && make clean && cd ../..
$(MAKE) -C corev_apu/fpga clean
$(MAKE) -C corev_apu/fpga/src/bootrom BOARD=$(BOARD) XLEN=$(XLEN) clean
.PHONY:
build sim sim-verilate clean \

99
corev_apu/fpga/constraints/nexys_video.xdc Normal file
View file

@ -0,0 +1,99 @@
## Buttons
set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS15 } [get_ports { cpu_resetn }];
## On board single ended clock, 100MHz
set_property -dict { PACKAGE_PIN R4 IOSTANDARD LVCMOS33 } [get_ports { sys_clk_i }];
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports sys_clk_i]
## To use FT2232 JTAG
set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { trst_n }];
set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { tck }];
set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { tdi }];
set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { tdo }];
set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { tms }];
## UART
set_property -dict { PACKAGE_PIN AA19 IOSTANDARD LVCMOS33 } [get_ports { tx }];
set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { rx }];
## LEDs
set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS25 } [get_ports { led[0] }];
set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS25 } [get_ports { led[1] }];
set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS25 } [get_ports { led[2] }];
set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS25 } [get_ports { led[3] }];
set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS25 } [get_ports { led[4] }];
set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS25 } [get_ports { led[5] }];
set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS25 } [get_ports { led[6] }];
set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS25 } [get_ports { led[7] }];
## Switches
set_property -dict { PACKAGE_PIN E22 IOSTANDARD LVCMOS12 } [get_ports { sw[0] }];
set_property -dict { PACKAGE_PIN F21 IOSTANDARD LVCMOS12 } [get_ports { sw[1] }];
set_property -dict { PACKAGE_PIN G21 IOSTANDARD LVCMOS12 } [get_ports { sw[2] }];
set_property -dict { PACKAGE_PIN G22 IOSTANDARD LVCMOS12 } [get_ports { sw[3] }];
set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS12 } [get_ports { sw[4] }];
set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS12 } [get_ports { sw[5] }];
set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS12 } [get_ports { sw[6] }];
set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS12 } [get_ports { sw[7] }];
## Fan PWM
set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS25 } [get_ports { fan_pwm }];
## Ethernet
set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports { eth_rst_n }]; #IO_25_34 Sch=eth_rst_b
set_property -dict { PACKAGE_PIN AA14 IOSTANDARD LVCMOS25 } [get_ports { eth_txck }]; #IO_L5N_T0_13 Sch=eth_txck
set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS25 } [get_ports { eth_txctl }]; #IO_L10P_T1_13 Sch=eth_txctl
set_property -dict { PACKAGE_PIN Y12 IOSTANDARD LVCMOS25 } [get_ports { eth_txd[0] }]; #IO_L11N_T1_SRCC_13 Sch=eth_txd[0]
set_property -dict { PACKAGE_PIN W12 IOSTANDARD LVCMOS25 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_13 Sch=eth_txd[1]
set_property -dict { PACKAGE_PIN W11 IOSTANDARD LVCMOS25 } [get_ports { eth_txd[2] }]; #IO_L12P_T1_MRCC_13 Sch=eth_txd[2]
set_property -dict { PACKAGE_PIN Y11 IOSTANDARD LVCMOS25 } [get_ports { eth_txd[3] }]; #IO_L11P_T1_SRCC_13 Sch=eth_txd[3]
set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS25 } [get_ports { eth_rxck }]; #IO_L13P_T2_MRCC_13 Sch=eth_rxck
set_property -dict { PACKAGE_PIN W10 IOSTANDARD LVCMOS25 } [get_ports { eth_rxctl }]; #IO_L10N_T1_13 Sch=eth_rxctl
set_property -dict { PACKAGE_PIN AB16 IOSTANDARD LVCMOS25 } [get_ports { eth_rxd[0] }]; #IO_L2P_T0_13 Sch=eth_rxd[0]
set_property -dict { PACKAGE_PIN AA15 IOSTANDARD LVCMOS25 } [get_ports { eth_rxd[1] }]; #IO_L4P_T0_13 Sch=eth_rxd[1]
set_property -dict { PACKAGE_PIN AB15 IOSTANDARD LVCMOS25 } [get_ports { eth_rxd[2] }]; #IO_L4N_T0_13 Sch=eth_rxd[2]
set_property -dict { PACKAGE_PIN AB11 IOSTANDARD LVCMOS25 } [get_ports { eth_rxd[3] }]; #IO_L7P_T1_13 Sch=eth_rxd[3]
set_property -dict { PACKAGE_PIN AA16 IOSTANDARD LVCMOS25 } [get_ports { eth_mdc }]; #IO_L1N_T0_13 Sch=eth_mdc
set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS25 } [get_ports { eth_mdio }]; #IO_L1P_T0_13 Sch=eth_mdio
#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS25 } [get_ports { eth_pme_b }]; #IO_L6P_T0_13 Sch=eth_pme_b
#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS25 } [get_ports { eth_int_b }]; #IO_L6N_T0_VREF_13 Sch=eth_int_b
#############################################
# Ethernet Constraints for 1Gb/s
#############################################
# Modified for 125MHz receive clock
# create_clock -period 8.000 -name eth_rxck [get_ports eth_rxck]
# set_clock_groups -asynchronous -group [get_clocks eth_rxck -include_generated_clocks]
# set_clock_groups -asynchronous -group [get_clocks clk_out2_xlnx_clk_gen]
## SD card
set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { spi_clk_o }]; #IO_L12P_T1_MRCC_14 Sch=sd_cclk
set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { spi_ss }]; #IO_L18N_T2_A11_D27_14 Sch=sd_d[3]
set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports { spi_miso }]; #IO_L14N_T2_SRCC_14 Sch=sd_d[0]
set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 } [get_ports { spi_mosi }]; #IO_L12N_T1_MRCC_14 Sch=sd_cmd
#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L20N_T3_A07_D23_14 Sch=sd_cd
#set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 } [get_ports { sd_d[1] }]; #IO_L4P_T0_D04_14 Sch=sd_d[1]
#set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { sd_d[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sd_d[2]
#set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L11N_T1_SRCC_14 Sch=sd_reset
# Nexys Video has a quad SPI flash
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
## JTAG
# minimize routing delay
set_max_delay -to [get_ports { tdo } ] 20
set_max_delay -from [get_ports { tms } ] 20
set_max_delay -from [get_ports { tdi } ] 20
set_max_delay -from [get_ports { trst_n } ] 20
# reset signal
set_false_path -from [get_ports { trst_n } ]
set_false_path -from [get_pins i_ddr/u_xlnx_mig_7_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C]
## Configuration options, can be used for all designs
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

6
corev_apu/fpga/scripts/run.tcl
View file

@ -22,6 +22,8 @@ if {$::env(BOARD) eq "genesys2"} {
add_files -fileset constrs_1 -norecurse constraints/kc705.xdc
} elseif {$::env(BOARD) eq "vc707"} {
add_files -fileset constrs_1 -norecurse constraints/vc707.xdc
} elseif {$::env(BOARD) eq "nexys_video"} {
add_files -fileset constrs_1 -norecurse constraints/nexys_video.xdc
} else {
exit 1
}
@ -63,6 +65,10 @@ if {$::env(BOARD) eq "genesys2"} {
read_verilog -sv {src/vc707.svh ../../vendor/pulp-platform/common_cells/include/common_cells/registers.svh}
set file "src/vc707.svh"
set registers "../../vendor/pulp-platform/common_cells/include/common_cells/registers.svh"
} elseif {$::env(BOARD) eq "nexys_video"} {
read_verilog -sv {src/nexys_video.svh ../../vendor/pulp-platform/common_cells/include/common_cells/registers.svh}
set file "src/nexys_video.svh"
set registers "../../vendor/pulp-platform/common_cells/include/common_cells/registers.svh"
} else {
exit 1
}

2
corev_apu/fpga/scripts/write_cfgmem.tcl
View file

@ -32,6 +32,8 @@ if {$::env(BOARD) eq "genesys2"} {
write_cfgmem -format mcs -interface bpix16 -size 128 -loadbit "up 0x0 $bitfile" -file $mcsfile -force
} elseif {$::env(BOARD) eq "kc705"} {
write_cfgmem -format mcs -interface SPIx4 -size 128 -loadbit "up 0x0 $bitfile" -file $mcsfile -force
} elseif {$::env(BOARD) eq "nexys_video"} {
write_cfgmem -format mcs -interface SPIx4 -size 256 -loadbit "up 0x0 $bitfile" -file $mcsfile -force
} else {
exit 1
}

8
corev_apu/fpga/sourceme.sh
View file

@ -28,3 +28,11 @@ if [ "$BOARD" = "vc707" ]; then
export XILINX_BOARD="xilinx.com:vc707:part0:1.3"
export CLK_PERIOD_NS="20"
fi
if [ "$BOARD" = "nexys_video" ]; then
echo -n "Configuring for "
echo "Nexys Video Artix-7"
export XILINX_PART="xc7a200tsbg484-1"
export XILINX_BOARD="digilentinc.com:nexys_video:part0:1.1"
export CLK_PERIOD_NS="40"
fi

136
corev_apu/fpga/src/ariane_xilinx.sv
View file

@ -138,6 +138,38 @@ module ariane_xilinx (
input wire [7:0] pci_exp_rxp ,
input wire [7:0] pci_exp_rxn ,
input logic trst_n ,
`elsif NEXYS_VIDEO
input logic sys_clk_i ,
input logic cpu_resetn ,
inout wire [15:0] ddr3_dq ,
inout wire [ 1:0] ddr3_dqs_n ,
inout wire [ 1:0] ddr3_dqs_p ,
output wire [14:0] ddr3_addr ,
output wire [ 2:0] ddr3_ba ,
output wire ddr3_ras_n ,
output wire ddr3_cas_n ,
output wire ddr3_we_n ,
output wire ddr3_reset_n,
output wire [ 0:0] ddr3_ck_p ,
output wire [ 0:0] ddr3_ck_n ,
output wire [ 0:0] ddr3_cke ,
output wire [ 1:0] ddr3_dm ,
output wire [ 0:0] ddr3_odt ,
output wire eth_rst_n ,
input wire eth_rxck ,
input wire eth_rxctl ,
input wire [3:0] eth_rxd ,
output wire eth_txck ,
output wire eth_txctl ,
output wire [3:0] eth_txd ,
inout wire eth_mdio ,
output logic eth_mdc ,
output logic [ 7:0] led ,
input logic [ 7:0] sw ,
output logic fan_pwm ,
input logic trst_n ,
`endif
// SPI
output logic spi_mosi ,
@ -243,6 +275,9 @@ assign cpu_resetn = ~cpu_reset;
`elsif VC707
assign cpu_resetn = ~cpu_reset;
assign trst_n = ~trst;
`elsif NEXYS_VIDEO
logic cpu_reset;
assign cpu_reset = ~cpu_resetn;
`endif
logic pll_locked;
@ -819,6 +854,8 @@ end
logic [3:0] unused_switches = 4'b0000;
`endif
logic clk_200MHz_ref;
ariane_peripherals #(
.AxiAddrWidth ( AxiAddrWidth ),
.AxiDataWidth ( AxiDataWidth ),
@ -838,10 +875,13 @@ ariane_peripherals #(
`elsif VCU118
.InclSPI ( 1'b0 ),
.InclEthernet ( 1'b0 )
`elsif NEXYS_VIDEO
.InclSPI ( 1'b1 ),
.InclEthernet ( 1'b0 )
`endif
) i_ariane_peripherals (
.clk_i ( clk ),
.clk_200MHz_i ( ddr_clock_out ),
.clk_200MHz_i ( clk_200MHz_ref ),
.rst_ni ( ndmreset_n ),
.plic ( master[ariane_soc::PLIC] ),
.uart ( master[ariane_soc::UART] ),
@ -1089,6 +1129,20 @@ xlnx_axi_clock_converter i_xlnx_axi_clock_converter_ddr (
.m_axi_rready ( s_axi_rready )
);
`ifdef NEXYS_VIDEO
xlnx_clk_gen i_xlnx_clk_gen (
.clk_out1 ( clk ), // 25 MHz
.clk_out2 ( phy_tx_clk ), // 125 MHz (for RGMII PHY)
.clk_out3 ( eth_clk ), // 125 MHz quadrature (90 deg phase shift)
.clk_out4 ( sd_clk_sys ), // 50 MHz clock
.clk_out5 ( clk_200MHz_ref ), // 200 MHz clock
.reset ( cpu_reset ),
.locked ( pll_locked ),
.clk_in1 ( ddr_clock_out ) // 100MHz input clock
);
`else
xlnx_clk_gen i_xlnx_clk_gen (
.clk_out1 ( clk ), // 50 MHz
.clk_out2 ( phy_tx_clk ), // 125 MHz (for RGMII PHY)
@ -1098,6 +1152,9 @@ xlnx_clk_gen i_xlnx_clk_gen (
.locked ( pll_locked ),
.clk_in1 ( ddr_clock_out )
);
assign clk_200MHz_ref = ddr_clock_out;
`endif
`ifdef KINTEX7
fan_ctrl i_fan_ctrl (
@ -1253,6 +1310,83 @@ xlnx_mig_7_ddr3 i_ddr (
.device_temp ( ), // keep open
.sys_rst ( cpu_resetn )
);
`elsif NEXYS_VIDEO
fan_ctrl i_fan_ctrl (
.clk_i ( clk ),
.rst_ni ( ndmreset_n ),
.pwm_setting_i ( '1 ),
.fan_pwm_o ( fan_pwm )
);
xlnx_mig_7_ddr3 i_ddr (
.sys_clk_i ( sys_clk_i ),
.clk_ref_i ( clk_200MHz_ref ),
.ddr3_dq,
.ddr3_dqs_n,
.ddr3_dqs_p,
.ddr3_addr,
.ddr3_ba,
.ddr3_ras_n,
.ddr3_cas_n,
.ddr3_we_n,
.ddr3_reset_n,
.ddr3_ck_p,
.ddr3_ck_n,
.ddr3_cke,
.ddr3_dm,
.ddr3_odt,
.mmcm_locked ( ), // keep open
.app_sr_req ( '0 ),
.app_ref_req ( '0 ),
.app_zq_req ( '0 ),
.app_sr_active ( ), // keep open
.app_ref_ack ( ), // keep open
.app_zq_ack ( ), // keep open
.ui_clk ( ddr_clock_out ),
.ui_clk_sync_rst ( ddr_sync_reset ),
.aresetn ( ndmreset_n ),
.s_axi_awid,
.s_axi_awaddr ( s_axi_awaddr[28:0] ),
.s_axi_awlen,
.s_axi_awsize,
.s_axi_awburst,
.s_axi_awlock,
.s_axi_awcache,
.s_axi_awprot,
.s_axi_awqos,
.s_axi_awvalid,
.s_axi_awready,
.s_axi_wdata,
.s_axi_wstrb,
.s_axi_wlast,
.s_axi_wvalid,
.s_axi_wready,
.s_axi_bready,
.s_axi_bid,
.s_axi_bresp,
.s_axi_bvalid,
.s_axi_arid,
.s_axi_araddr ( s_axi_araddr[28:0] ),
.s_axi_arlen,
.s_axi_arsize,
.s_axi_arburst,
.s_axi_arlock,
.s_axi_arcache,
.s_axi_arprot,
.s_axi_arqos,
.s_axi_arvalid,
.s_axi_arready,
.s_axi_rready,
.s_axi_rid,
.s_axi_rdata,
.s_axi_rresp,
.s_axi_rlast,
.s_axi_rvalid,
.init_calib_complete ( ), // keep open
.device_temp ( ), // keep open
.sys_rst ( cpu_resetn )
);
`elsif VCU118
logic [63:0] dram_dwidth_axi_awaddr;

4
corev_apu/fpga/src/bootrom/.gitignore vendored
View file

@ -3,3 +3,7 @@ venv
*.o
*.img
*.bin
*.dts
*.dtb
bootrom*.h
bootrom*.sv

48
corev_apu/fpga/src/bootrom/Makefile
View file

@ -1,11 +1,31 @@
XLEN ?= 64
CROSSCOMPILE ?= riscv64-unknown-elf-
CC = ${CROSSCOMPILE}gcc
CROSSCOMPILE ?= riscv-none-elf-
ifeq ($(BOARD), nexys_video)
DRAM_SIZE_64 ?= 0x20000000 #512MB
DRAM_SIZE_32 ?= 0x08000000 #128MB
CLOCK_FREQUENCY ?= 25000000 #25MHz
HALF_CLOCK_FREQUENCY ?= 12500000 #12.5MHz
UART_BITRATE ?= 57600
HAS_ETHERNET ?= 0
else
DRAM_SIZE_64 ?= 0x40000000 #1GB
DRAM_SIZE_32 ?= 0x08000000 #128MB
CLOCK_FREQUENCY ?= 50000000 #50MHz
HALF_CLOCK_FREQUENCY ?= 25000000 #25MHz
UART_BITRATE ?= 115200
HAS_ETHERNET ?= 1
endif
CC = $(RISCV)/bin/${CROSSCOMPILE}gcc
OBJCOPY = $(RISCV)/bin/$(CROSSCOMPILE)objcopy
SED = sed
PLATFORM_DEFINES = -DCLOCK_FREQUENCY=$(CLOCK_FREQUENCY) -DUART_BITRATE=$(UART_BITRATE)
ifeq ($(XLEN), 64)
CFLAGS = -Os -ggdb -march=rv64imac -mabi=lp64 -Wall -mcmodel=medany -mexplicit-relocs
CFLAGS = $(PLATFORM_DEFINES) -Os -ggdb -march=rv64imac_zba_zbb_zbs_zbc_zicsr_zifencei -mabi=lp64 -Wall -mcmodel=medany -mexplicit-relocs -ffreestanding
else
CFLAGS = -O2 -ggdb -march=rv32im -mabi=ilp32 -W -Wall -mcmodel=medany -mexplicit-relocs -fno-builtin
CFLAGS = $(PLATFORM_DEFINES) -O2 -ggdb -march=rv32imac_zba_zbb_zbs_zbc_zicsr_zifencei -mabi=ilp32 -W -Wall -mcmodel=medany -mexplicit-relocs -fno-builtin -ffreestanding
endif
CCASFLAGS = -mcmodel=medany -mexplicit-relocs
@ -25,6 +45,12 @@ MAIN_SV = $(MAIN:.elf=.sv)
DTB = cv$(XLEN)a6.dtb
ifeq ($(HAS_ETHERNET), 1)
SED_DELETE_OPT = -e "/DELETE_ETH/d"
else
SED_DELETE_OPT =
endif
#.PHONY: clean
$(MAIN): $(DTB) $(OBJS_C) $(OBJS_S) linker.lds
@ -35,7 +61,7 @@ $(MAIN): $(DTB) $(OBJS_C) $(OBJS_S) linker.lds
dd if=$< of=$@ bs=128
%.bin: %.elf
$(CROSSCOMPILE)objcopy -O binary $< $@
$(OBJCOPY) -O binary $< $@
%.o: %.c
@$(CC) $(CFLAGS) $(INCLUDES) -c $< -o $@
@ -45,6 +71,15 @@ $(MAIN): $(DTB) $(OBJS_C) $(OBJS_S) linker.lds
@$(CC) $(CFLAGS) $(CCASFLAGS) $(INCLUDES) -c $< -o $@
@echo "CC <= $<"
%.dts: %.dts.in
$(SED) -e "s/DRAM_SIZE_64/$(DRAM_SIZE_64)/g" \
-e "s/DRAM_SIZE_32/$(DRAM_SIZE_32)/g" \
-e "s/HALF_CLOCK_FREQUENCY/$(HALF_CLOCK_FREQUENCY)/g" \
-e "s/CLOCK_FREQUENCY/$(CLOCK_FREQUENCY)/g" \
-e "s/UART_BITRATE/$(UART_BITRATE)/g" \
$(SED_DELETE_OPT) $< > $@
cat $@
%.dtb: %.dts
dtc -I dts $< -O dtb -o $@
@ -53,7 +88,8 @@ $(MAIN): $(DTB) $(OBJS_C) $(OBJS_S) linker.lds
@echo "PYTHON >= $(MAIN_SV)"
clean:
$(RM) $(OBJS_C) $(OBJS_S) $(MAIN) $(MAIN_BIN) $(MAIN_IMG) *.dtb
$(RM) $(OBJS_C) $(OBJS_S) $(MAIN) $(MAIN_BIN) $(MAIN_IMG) *.dtb *.dts *.sv
rm -f ./bootrom_32.h ./bootrom_64.h
all: $(MAIN) $(MAIN_BIN) $(MAIN_IMG) $(MAIN_SV)
@echo "zero stage bootloader has been compiled!"

1982
corev_apu/fpga/src/bootrom/bootrom_32.h
View file

File diff suppressed because it is too large Load diff

1027
corev_apu/fpga/src/bootrom/bootrom_32.sv
View file

File diff suppressed because it is too large Load diff

1796
corev_apu/fpga/src/bootrom/bootrom_64.h
View file

File diff suppressed because it is too large Load diff

934
corev_apu/fpga/src/bootrom/bootrom_64.sv
View file

@ -1,934 +0,0 @@
/* Copyright 2018 ETH Zurich and University of Bologna.
* Copyright and related rights are licensed under the Solderpad Hardware
* License, Version 0.51 (the "License"); you may not use this file except in
* compliance with the License. You may obtain a copy of the License at
* http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
* or agreed to in writing, software, hardware and materials distributed under
* this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
* CONDITIONS OF ANY KIND, either express or implied. See the License for the
* specific language governing permissions and limitations under the License.
*
* File: $filename.v
*
* Description: Auto-generated bootrom
*/
// Auto-generated code
module bootrom_64 (
input logic clk_i,
input logic req_i,
input logic [63:0] addr_i,
output logic [63:0] rdata_o
);
localparam int RomSize = 895;
const logic [RomSize-1:0][63:0] mem = {
64'h00000000_00000000,
64'h0a0d2165_6e6f6420,
64'h00000000_00206567,
64'h616d6920_746f6f62,
64'h20676e69_79706f63,
64'h00000000_00000009,
64'h3a656d61_6e090a0d,
64'h00093a73_65747562,
64'h69727474_61090a0d,
64'h00000009_3a61626c,
64'h20747361_6c090a0d,
64'h0000093a_61626c20,
64'h74737269_66090a0d,
64'h00000000_00000000,
64'h09202020_20203a64,
64'h69756720_6e6f6974,
64'h69747261_70090a0d,
64'h00000000_00000000,
64'h093a6469_75672065,
64'h70797420_6e6f6974,
64'h69747261_70090a0d,
64'h00000000_20797274,
64'h6e65206e_6f697469,
64'h74726170_20747067,
64'h00000009_20203a73,
64'h65697274_6e65206e,
64'h6f697469_74726170,
64'h20657a69_73090a0d,
64'h00000009_3a736569,
64'h72746e65_206e6f69,
64'h74697472_61702072,
64'h65626d75_6e090a0d,
64'h00000009_2020203a,
64'h61626c20_73656972,
64'h746e6520_6e6f6974,
64'h69747261_70090a0d,
64'h00093a61_646c2070,
64'h756b6361_62090a0d,
64'h00000000_00000000,
64'h093a6162_6c20746e,
64'h65727275_63090a0d,
64'h00000009_3a646576,
64'h72657365_72090a0d,
64'h00093a72_65646165,
64'h685f6372_63090a0d,
64'h00000000_00000909,
64'h3a657a69_73090a0d,
64'h00000009_3a6e6f69,
64'h73697665_72090a0d,
64'h0000093a_65727574,
64'h616e6769_73090a0d,
64'h00000000_003a7265,
64'h64616568_20656c62,
64'h6174206e_6f697469,
64'h74726170_20747067,
64'h0000203a_65756c61,
64'h76206e72_75746572,
64'h2079706f_63206473,
64'h00000000_0000000a,
64'h0d216465_6c696166,
64'h20647261_63204453,
64'h00000000_0000000a,
64'h0d216465_7a696c61,
64'h6974696e_69206473,
64'h00000000_0a0d676e,
64'h69746978_65202e2e,
64'h2e647320_657a696c,
64'h61697469_6e692074,
64'h6f6e2064_6c756f63,
64'h00000000_0000002e,
64'h00000000_0000000a,
64'h0d6b636f_6c622044,
64'h53206461_65722074,
64'h6f6e2064_6c756f63,
64'h0000000a_0d202e2e,
64'h2e445320_676e697a,
64'h696c6169_74696e69,
64'h00000031_34646d63,
64'h00000035_35646d63,
64'h00000000_30646d63,
64'h00000020_3a206573,
64'h6e6f7073_65720920,
64'h00000000_0020646e,
64'h616d6d6f_63204453,
64'h00000000_203f3f79,
64'h74706d65_20746f6e,
64'h206f6669_66207872,
64'h00000000_00000a0d,
64'h2164657a_696c6169,
64'h74696e69_20495053,
64'h00000000_00007830,
64'h203a7375_74617473,
64'h00000000_00000a0d,
64'h49505320_74696e69,
64'h00000a0d_21646c72,
64'h6f57206f_6c6c6548,
64'h00000000_00000032,
64'h2d746c75_61666564,
64'h2d697274_2c786e6c,
64'h7800746c_75616665,
64'h642d6972_742c786e,
64'h6c78006c_6175642d,
64'h73692c78_6e6c7800,
64'h746e6573_6572702d,
64'h74707572_7265746e,
64'h692c786e_6c780068,
64'h74646977_2d326f69,
64'h70672c78_6e6c7800,
64'h68746469_772d6f69,
64'h70672c78_6e6c7800,
64'h322d746c_75616665,
64'h642d7475_6f642c78,
64'h6e6c7800_746c7561,
64'h6665642d_74756f64,
64'h2c786e6c_7800322d,
64'h73747570_6e692d6c,
64'h6c612c78_6e6c7800,
64'h73747570_6e692d6c,
64'h6c612c78_6e6c7800,
64'h72656c6c_6f72746e,
64'h6f632d6f_69706700,
64'h736c6c65_632d6f69,
64'h70672300_73736572,
64'h6464612d_63616d2d,
64'h6c61636f_6c007077,
64'h2d656c62_61736964,
64'h00736567_6e61722d,
64'h65676174_6c6f7600,
64'h79636e65_75716572,
64'h662d7861_6d2d6970,
64'h73006f69_7461722d,
64'h6b63732c_786e6c78,
64'h00737469_622d7265,
64'h66736e61_72742d6d,
64'h756e2c78_6e6c7800,
64'h73746962_2d73732d,
64'h6d756e2c_786e6c78,
64'h00747369_78652d6f,
64'h6669662c_786e6c78,
64'h00796c69_6d61662c,
64'h786e6c78_00687464,
64'h69772d6f_692d6765,
64'h72007466_6968732d,
64'h67657200_73747075,
64'h72726574_6e690074,
64'h6e657261_702d7470,
64'h75727265_746e6900,
64'h64656570_732d746e,
64'h65727275_63007665,
64'h646e2c76_63736972,
64'h00797469_726f6972,
64'h702d7861_6d2c7663,
64'h73697200_73656d61,
64'h6e2d6765_72006465,
64'h646e6574_78652d73,
64'h74707572_7265746e,
64'h69007365_676e6172,
64'h00646564_6e657073,
64'h75732d65_74617473,
64'h2d6e6961_74657200,
64'h72656767_6972742d,
64'h746c7561_6665642c,
64'h78756e69_6c00736f,
64'h69706700_656c646e,
64'h61687000_72656c6c,
64'h6f72746e_6f632d74,
64'h70757272_65746e69,
64'h00736c6c_65632d74,
64'h70757272_65746e69,
64'h23007469_6c70732d,
64'h626c7400_65707974,
64'h2d756d6d_00617369,
64'h2c766373_69720073,
64'h75746174_73006765,
64'h72006570_79745f65,
64'h63697665_64007963,
64'h6e657571_6572662d,
64'h6b636f6c_63007963,
64'h6e657571_6572662d,
64'h65736162_656d6974,
64'h00687461_702d7475,
64'h6f647473_006c6564,
64'h6f6d0065_6c626974,
64'h61706d6f_6300736c,
64'h6c65632d_657a6973,
64'h2300736c_6c65632d,
64'h73736572_64646123,
64'h09000000_02000000,
64'h02000000_02000000,
64'h01000000_b5000000,
64'h04000000_03000000,
64'hffffffff_bf020000,
64'h04000000_03000000,
64'hffffffff_ae020000,
64'h04000000_03000000,
64'h01000000_a1020000,
64'h04000000_03000000,
64'h00000000_8a020000,
64'h04000000_03000000,
64'h08000000_79020000,
64'h04000000_03000000,
64'h08000000_69020000,
64'h04000000_03000000,
64'h00000000_55020000,
64'h04000000_03000000,
64'h00000000_43020000,
64'h04000000_03000000,
64'h00000000_31020000,
64'h04000000_03000000,
64'h00000000_21020000,
64'h04000000_03000000,
64'h00000100_00000000,
64'h00000040_00000000,
64'h67000000_10000000,
64'h03000000_11020000,
64'h00000000_03000000,
64'h00000000_612e3030,
64'h2e312d6f_6970672d,
64'h7370782c_786e6c78,
64'h1b000000_15000000,
64'h03000000_02000000,
64'h05020000_04000000,
64'h03000000_00000030,
64'h30303030_30303440,
64'h6f697067_01000000,
64'h02000000_00800000,
64'h00000000_00000030,
64'h00000000_67000000,
64'h10000000_03000000,
64'h00007fe3_023e1800,
64'hf3010000_06000000,
64'h03000000_00000000,
64'h03000000_52010000,
64'h08000000_03000000,
64'h03000000_41010000,
64'h04000000_03000000,
64'h006b726f_7774656e,
64'h5b000000_08000000,
64'h03000000_00687465,
64'h2d637369_72776f6c,
64'h1b000000_0c000000,
64'h03000000_00000000,
64'h30303030_30303033,
64'h40687465_2d637369,
64'h72776f6c_01000000,
64'h02000000_02000000,
64'he8010000_00000000,
64'h03000000_e40c0000,
64'he40c0000_d9010000,
64'h08000000_03000000,
64'h20bcbe00_c7010000,
64'h04000000_03000000,
64'h00000000_67000000,
64'h04000000_03000000,
64'h00000000_746f6c73,
64'h2d697073_2d636d6d,
64'h1b000000_0d000000,
64'h03000000_00000030,
64'h40636d6d_01000000,
64'h04000000_b8010000,
64'h04000000_03000000,
64'h08000000_a1010000,
64'h04000000_03000000,
64'h01000000_90010000,
64'h04000000_03000000,
64'h01000000_80010000,
64'h04000000_03000000,
64'h00377865_746e696b,
64'h74010000_08000000,
64'h03000000_00100000,
64'h00000000_00000020,
64'h00000000_67000000,
64'h10000000_03000000,
64'h02000000_02000000,
64'h52010000_08000000,
64'h03000000_03000000,
64'h41010000_04000000,
64'h03000000_00000000,
64'h0f000000_04000000,
64'h03000000_01000000,
64'h00000000_04000000,
64'h03000000_00612e30,
64'h302e322d_6970732d,
64'h7370782c_786e6c78,
64'h00622e30_302e322d,
64'h6970732d_7370782c,
64'h786e6c78_1b000000,
64'h28000000_03000000,
64'h00000000_30303030,
64'h30303032_40697073,
64'h2d737078_01000000,
64'h02000000_006c6f72,
64'h746e6f63_0b010000,
64'h08000000_03000000,
64'h03000000_41010000,
64'h04000000_03000000,
64'h00100000_00000000,
64'h00000018_00000000,
64'h67000000_10000000,
64'h03000000_07000000,
64'h06000000_05000000,
64'h04000000_52010000,
64'h10000000_03000000,
64'h00007265_6d69745f,
64'h6270612c_706c7570,
64'h1b000000_0f000000,
64'h03000000_00003030,
64'h30303030_38314072,
64'h656d6974_01000000,
64'h02000000_04000000,
64'h67010000_04000000,
64'h03000000_02000000,
64'h5d010000_04000000,
64'h03000000_01000000,
64'h52010000_04000000,
64'h03000000_03000000,
64'h41010000_04000000,
64'h03000000_00c20100,
64'h33010000_04000000,
64'h03000000_80f0fa02,
64'h4b000000_04000000,
64'h03000000_00100000,
64'h00000000_00000010,
64'h00000000_67000000,
64'h10000000_03000000,
64'h00000000_61303535,
64'h3631736e_1b000000,
64'h09000000_03000000,
64'h00000030_30303030,
64'h30303140_74726175,
64'h01000000_02000000,
64'h03000000_b5000000,
64'h04000000_03000000,
64'h1e000000_28010000,
64'h04000000_03000000,
64'h07000000_15010000,
64'h04000000_03000000,
64'h00000004_00000000,
64'h0000000c_00000000,
64'h67000000_10000000,
64'h03000000_09000000,
64'h02000000_0b000000,
64'h02000000_f7000000,
64'h10000000_03000000,
64'ha0000000_00000000,
64'h03000000_00306369,
64'h6c702c76_63736972,
64'h1b000000_0c000000,
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64'h00000000_04000000,
64'h03000000_00000000,
64'h30303030_30306340,
64'h72656c6c_6f72746e,
64'h6f632d74_70757272,
64'h65746e69_01000000,
64'h02000000_006c6f72,
64'h746e6f63_0b010000,
64'h08000000_03000000,
64'h00000c00_00000000,
64'h00000002_00000000,
64'h67000000_10000000,
64'h03000000_07000000,
64'h02000000_03000000,
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64'h10000000_03000000,
64'h00000000_30746e69,
64'h6c632c76_63736972,
64'h1b000000_0d000000,
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64'h6e696c63_01000000,
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64'h04000000_03000000,
64'h00636f73_01000000,
64'h02000000_02000000,
64'hd9000000_00000000,
64'h03000000_00000074,
64'h61656274_72616568,
64'hc3000000_0a000000,
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64'h72616568_01000000,
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64'h00000000_7364656c,
64'h01000000_02000000,
64'h00000040_00000000,
64'h00000080_00000000,
64'h67000000_10000000,
64'h03000000_00007972,
64'h6f6d656d_5b000000,
64'h07000000_03000000,
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64'h38407972_6f6d656d,
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64'h6f72746e_6f632d74,
64'h70757272_65746e69,
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64'h63736972_7c000000,
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64'h40757063_01000000,
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64'h04000000_03000000,
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64'h30314074_7261752f,
64'h636f732f_2c000000,
64'h1a000000_03000000,
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64'h01000000_00657261,
64'h622d656e_61697261,
64'h2c687465_26000000,
64'h10000000_03000000,
64'h00766564_2d657261,
64'h622d656e_61697261,
64'h2c687465_1b000000,
64'h14000000_03000000,
64'h02000000_0f000000,
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64'h04000000_03000000,
64'h00000000_01000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'he8080000_d2020000,
64'h00000000_10000000,
64'h11000000_28000000,
64'h20090000_38000000,
64'hf20b0000_edfe0dd0,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h46454443_42413938,
64'h37363534_33323130,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h0000a001_84021ae5,
64'h85930000_0597047e,
64'h0010041b_e909c6bf,
64'hf0ef057e_65a14505,
64'he38ff0ef_dc450513,
64'h00001517_e00ff0ef,
64'he4060805_05132005,
64'h85931141_02faf537,
64'h65f1b79d_f8c371e3,
64'h963e8f1d_17c18096,
64'hfa2680e7_82869696,
64'h00000297_00279693,
64'hb7598dd5_02059693,
64'h8dd50105_96938dd5,
64'h00859693_0ff5f593,
64'h808200b7_002300b7,
64'h00a300b7_012300b7,
64'h01a300b7_022300b7,
64'h02a300b7_032300b7,
64'h03a300b7_042300b7,
64'h04a300b7_052300b7,
64'h05a300b7_062300b7,
64'h06a300b7_072300a6,
64'h80679696_00000297,
64'h068a40c3_06b38082,
64'he211fed7_6de30741,
64'he70ce30c_96ba8a3d,
64'hff067693_e1bde3c1,
64'h00f77793_02c37163,
64'h872a433d_b3b5f06f,
64'hf0ef1825_05130000,
64'h1517bbf1_edc50513,
64'h00001517_f9eff0ef,
64'h854af22f_f0effde5,
64'h05130000_1517f2ef,
64'hf0effd25_05130000,
64'h1517b511_f0450513,
64'h00001517_fc6ff0ef,
64'h8526f4af_f0ef0065,
64'h05130000_1517f56f,
64'hf0efffa5_05130000,
64'h1517c929_84aac5bf,
64'hf0ef9e0d_26058552,
64'h020aa583_028ab603,
64'hf78ff0ef_1dc50513,
64'h00001517_f56910e3,
64'h08048493_f8cff0ef,
64'h2905f5a5_05130000,
64'h1517ff89_9be3863f,
64'hf0ef0985_0009c503,
64'hfa8ff0ef_1fc50513,
64'h00001517_837ff0ef,
64'h6888fbaf_f0ef1fe5,
64'h05130000_1517849f,
64'hf0ef6488_fccff0ef,
64'h20050513_00001517,
64'h85bff0ef_06048c13,
64'h01848993_6088fe6f,
64'hf0ef20a5_05130000,
64'h1517ff34_9be38bbf,
64'hf0ef0985_0009c503,
64'hff048993_805ff0ef,
64'h20850513_00001517,
64'hff7999e3_8d9ff0ef,
64'h09850007_c503013c,
64'h07b34981_825ff0ef,
64'hfe048c13_20c50513,
64'h00001517_8f9ff0ef,
64'h0ff97513_83dff0ef,
64'h20850513_00001517,
64'h4b114bc1_10051b63,
64'h1004892a_8a8ad4bf,
64'hf0ef850a_46057101,
64'h04892583_865ff0ef,
64'h03050513_00001517,
64'h8b3ff0ef_4556877f,
64'hf0ef2225_05130000,
64'h15178c5f_f0ef4546,
64'h889ff0ef_21450513,
64'h00001517_917ff0ef,
64'h652689bf_f0ef2065,
64'h05130000_1517929f,
64'hf0ef7502_8adff0ef,
64'h20850513_00001517,
64'h93bff0ef_65628bff,
64'hf0ef2025_05130000,
64'h151790df_f0ef4552,
64'h8d1ff0ef_20450513,
64'h00001517_91fff0ef,
64'h45428e3f_f0ef2065,
64'h05130000_1517931f,
64'hf0ef4532_8f5ff0ef,
64'h20850513_00001517,
64'h943ff0ef_4522907f,
64'hf0ef20a5_05130000,
64'h1517995f_f0ef6502,
64'h919ff0ef_20c50513,
64'h00001517_925ff0ef,
64'h1f850513_00001517,
64'hbf6154f9_935ff0ef,
64'h10050513_00001517,
64'h9c3ff0ef_8526947f,
64'hf0ef2025_05130000,
64'h1517953f_f0ef1f65,
64'h05130000_1517c905,
64'h84aa890a_e59ff0ef,
64'h850a4585_46057101,
64'h971ff0ef_1fc50513,
64'h00001517_80826161,
64'h6c026ba2_6b426ae2,
64'h7a0279a2_794274e2,
64'h64068526_60a6fb04,
64'h011354fd_99dff0ef,
64'h20050513_00001517,
64'hc51de01f_f0ef8a2a,
64'h0880e062_e45ee85a,
64'hec56f44e_f84afc26,
64'he486f052_e0a2715d,
64'hb7655479_80826169,
64'h6baa6b4a_6aea7a0a,
64'h79aa794a_74ea640e,
64'h852260ae_547d9e7f,
64'hf0ef2225_05130000,
64'h1517c6bf_f0efc6ff,
64'hf0efc73f_f0efc77f,
64'hf0efc7bf_f0efc7ff,
64'hf0efc83f_f0efc87f,
64'hf0efa805_c8dff0ef,
64'hc97ff0ef_45314581,
64'h46054401_f92047e3,
64'h197da2bf_f0ef2865,
64'h05130000_1517e799,
64'h034967b3_06941a63,
64'h24819041_14428c49,
64'hcc1ff0ef_90411442,
64'h0085141b_8aa2ccff,
64'hf0effd64_1ae30404,
64'h0413ff7a_97e384aa,
64'hf25ff0ef_0a858526,
64'h0007c583_015407b3,
64'h04000b93_4a81c73f,
64'hf0ef850a_04000593,
64'h8622200a_8b134481,
64'h8456ff35_1ee3d0ff,
64'hf0ef3e80_0a130fe0,
64'h09930209_5913e959,
64'hd27ff0ef_454985a2,
64'h0ff67613_00166613,
64'h0015161b_f57ff0ef,
64'h0ff47593_f5fff0ef,
64'h0ff5f593_0084559b,
64'hf6bff0ef_0ff5f593,
64'h0104559b_f77ff0ef,
64'h45010184_559b3e60,
64'h00efe55e_e95af152,
64'hf54efd26_e5860800,
64'h0613850a_02061913,
64'h8aaa0ff0_0593ed56,
64'h842ef94a_e1a27155,
64'h80829141_15428d3d,
64'h8ff91781_0057171b,
64'h67890107_571b0105,
64'h171b8d3d_00c5179b,
64'h8d2d893d_0045d51b,
64'h8dbd93c1_17c28fc9,
64'h0085551b_0085179b,
64'h808207f5_75138d3d,
64'h0ff7f793_0045179b,
64'h8d2d0ff5_75138d3d,
64'h0045d51b_0075d79b,
64'h8de98082_0141853e,
64'h640260a2_57f5e111,
64'h4781f89f_f0efc511,
64'h57f9efdf_f0efc911,
64'h57fdeb9f_f0effc6d,
64'he09ff0ef_347d4429,
64'hb99ff0ef_3bc50513,
64'h00001517_c8dff0ef,
64'he022e406_11418082,
64'h61050015_351364a2,
64'h64420004_051b60e2,
64'hfc940ce3_e3dff0ef,
64'heb5ff0ef_3e450513,
64'h00001517_85aa842a,
64'he57ff0ef_02900513,
64'h400005b7_07700613,
64'hfbdff0ef_4485e822,
64'hec06e426_11018082,
64'h01410015_3513157d,
64'h64020004_051b60a2,
64'hef5ff0ef_41e50513,
64'h85a20000_1517e8ff,
64'hf0ef842a_e9bff0ef,
64'he022e406_03700513,
64'h45810650_06131141,
64'h80826105_690264a2,
64'h644260e2_00143513,
64'hf5640413_24010124,
64'h976388bd_00f91a63,
64'h45014785_ecdff0ef,
64'hed1ff0ef_842aed7f,
64'hf0ef84aa_eddff0ef,
64'hee1ff0ef_ee5ff0ef,
64'h892aef1f_f0efe04a,
64'he426e822_ec064521,
64'h1aa00593_08700613,
64'h1101bfcd_45018082,
64'h61056902_64a26442,
64'h60e24505_f89ff0ef,
64'h45854aa5_05130000,
64'h1517ff24_95e3c00d,
64'hf29ff0ef_84aa347d,
64'hf37ff0ef_45014581,
64'h09500613_49057104,
64'h0413e426_ec06e04a,
64'h6409e822_1101b9d1,
64'h61054a25_05130000,
64'h151764a2_60e26442,
64'hdadff0ef_8522ceff,
64'hf0ef4ea5_05130000,
64'h1517cfbf_f0ef8526,
64'hd01ff0ef_842ee822,
64'hec064f25_05130000,
64'h151784aa_e4261101,
64'h80826105_690264a2,
64'h644260e2_f47d147d,
64'h0007d463_4187d79b,
64'h0185179b_fadff0ef,
64'h06400413_ebbff0ef,
64'h8526ec1f_f0ef0ff4,
64'h7513ec9f_f0ef0ff5,
64'h75130084_551bed5f,
64'hf0ef0ff5_75130104,
64'h551bee1f_f0ef0184,
64'h551bee9f_f0ef0409,
64'h6513febf_f0ef892a,
64'he04a84b2_842ee426,
64'he822ec06_1101b709,
64'h0ff00513_8082557d,
64'hb7d900d7_00230785,
64'h00f60733_06c82683,
64'hff698b05_5178b77d,
64'hd6b80785_00074703,
64'h00f50733_80824501,
64'hd3b84719_dbb8577d,
64'h200007b7_02b6e163,
64'h0007869b_20000837,
64'h20000537_fff58b85,
64'h537c2000_0737d3b8,
64'h200007b7_10600713,
64'hfff537fd_00010320,
64'h079304b7_61630007,
64'h871b4781_200006b7,
64'hdbb85779_200007b7,
64'h06b7ee63_10000793,
64'h80826105_64a2d3b8,
64'h4719dbb8_64420ff4,
64'h7513577d_200007b7,
64'h60e2e2bf_f0ef5f65,
64'h05130000_1517eb9f,
64'hf0ef9101_15024088,
64'he41ff0ef_61450513,
64'h00001517_e3958b85,
64'h240153fc_57e0ff65,
64'h8b050647_849353f8,
64'hd3b81060_07132000,
64'h07b7fff5_37fd0001,
64'h06400793_d7a8dbb8,
64'h5779e426_e822ec06,
64'h200007b7_1101b551,
64'h61056425_05130000,
64'h151764a2_60e26442,
64'hd03c4799_e9dff0ef,
64'h66850513_00001517,
64'hf2bff0ef_91010204,
64'h95132481_eb5ff0ef,
64'h66050513_00001517,
64'h5064d03c_16600793,
64'hec9ff0ef_69450513,
64'h00001517_f57ff0ef,
64'h91010204_95132481,
64'hee1ff0ef_68c50513,
64'h00001517_5064d03c,
64'h10400793_20000437,
64'hfff537fd_000147a9,
64'hc3b84729_200007b7,
64'hf09ff0ef_e426e822,
64'hec066ac5_05131101,
64'h00001517_80824108,
64'h8082c10c_b5e96105,
64'h60e20091_4503ed7f,
64'hf0ef0081_4503f55f,
64'hf0efec06_002c1101,
64'h80826145_694264e2,
64'h740270a2_ff2410e3,
64'hef9ff0ef_00914503,
64'hf01ff0ef_34610081,
64'h4503f81f_f0ef0ff5,
64'h7513002c_0084d533,
64'h59610380_041384aa,
64'hf406e84a_ec26f022,
64'h71798082_61456942,
64'h64e27402_70a2ff24,
64'h10e3f3bf_f0ef0091,
64'h4503f43f_f0ef3461,
64'h00814503_fc3ff0ef,
64'h0ff57513_002c0084,
64'hd53b5961_446184aa,
64'hf406e84a_ec26f022,
64'h71798082_00f58023,
64'h0007c783_00e580a3,
64'h97aa8111_00074703,
64'h973e00f5_7713a6e7,
64'h87930000_1797b7f5,
64'h0405f93f_f0ef8082,
64'h01416402_60a2e509,
64'h00044503_842ae406,
64'he0221141_808200e7,
64'h88230200_071300e7,
64'h8423fc70_071300e7,
64'h8623470d_00a78223,
64'h0ff57513_00e78023,
64'h0085551b_0ff57713,
64'h00e78623_f8000713,
64'h00078223_100007b7,
64'h02b5553b_0045959b,
64'h808200a7_0023dfe5,
64'h0207f793_01474783,
64'h10000737_80820205,
64'h75130147_c5031000,
64'h07b78082_00054503,
64'h808200b5_00238082,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00048067_01f49493,
64'h0010049b_c8458593,
64'h00001597_f1402573,
64'hff24c6e3_4009091b,
64'h02000937_00448493,
64'hfe091ee3_0004a903,
64'h00092023_00990933,
64'h00291913_f1402973,
64'h020004b7_fe090ae3,
64'h00897913_34402973,
64'h10500073_ff24c6e3,
64'h4009091b_02000937,
64'h00448493_0124a023,
64'h00100913_020004b7,
64'h303000ef_01a11113,
64'h0210011b_03249663,
64'hf1402973_00000493,
64'h30491073_00800913
};
logic [$clog2(RomSize)-1:0] addr_q;
always_ff @(posedge clk_i) begin
if (req_i) begin
addr_q <= addr_i[$clog2(RomSize)-1+3:3];
end
end
// this prevents spurious Xes from propagating into
// the speculative fetch stage of the core
assign rdata_o = (addr_q < RomSize) ? mem[addr_q] : '0;
endmodule

14
corev_apu/fpga/src/bootrom/cv32a6.dts → corev_apu/fpga/src/bootrom/cv32a6.dts.in
View file

@ -6,14 +6,14 @@
compatible = "eth,ariane-bare-dev";
model = "eth,ariane-bare";
chosen {
stdout-path = "/soc/uart@10000000:115200";
stdout-path = "/soc/uart@10000000:UART_BITRATE";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <25000000>; // 25 MHz
timebase-frequency = <HALF_CLOCK_FREQUENCY>;
CPU0: cpu@0 {
clock-frequency = <50000000>; // 50 MHz
clock-frequency = <CLOCK_FREQUENCY>;
device_type = "cpu";
reg = <0>;
status = "okay";
@ -31,7 +31,7 @@
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x8000000>;
reg = <0x80000000 DRAM_SIZE_32>;
};
leds {
compatible = "gpio-leds";
@ -74,8 +74,8 @@
uart@10000000 {
compatible = "ns16550a";
reg = < 0x10000000 0x1000>;
clock-frequency = <50000000>;
current-speed = <115200>;
clock-frequency = <CLOCK_FREQUENCY>;
current-speed = <UART_BITRATE>;
interrupt-parent = <&PLIC0>;
interrupts = <1>;
reg-shift = <2>; // regs are spaced on 32 bit boundary
@ -144,3 +144,5 @@
};
};
};
// delete ethernet device if disabled
/delete-node/ &eth; // DELETE_ETH

14
corev_apu/fpga/src/bootrom/cv64a6.dts → corev_apu/fpga/src/bootrom/cv64a6.dts.in
View file

@ -6,14 +6,14 @@
compatible = "eth,ariane-bare-dev";
model = "eth,ariane-bare";
chosen {
stdout-path = "/soc/uart@10000000:115200";
stdout-path = "/soc/uart@10000000:UART_BITRATE";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <25000000>; // 25 MHz
timebase-frequency = <HALF_CLOCK_FREQUENCY>;
CPU0: cpu@0 {
clock-frequency = <50000000>; // 50 MHz
clock-frequency = <CLOCK_FREQUENCY>;
device_type = "cpu";
reg = <0>;
status = "okay";
@ -31,7 +31,7 @@
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x40000000>;
reg = <0x0 0x80000000 0x0 DRAM_SIZE_64>;
};
leds {
compatible = "gpio-leds";
@ -74,8 +74,8 @@
uart@10000000 {
compatible = "ns16550a";
reg = <0x0 0x10000000 0x0 0x1000>;
clock-frequency = <50000000>;
current-speed = <115200>;
clock-frequency = <CLOCK_FREQUENCY>;
current-speed = <UART_BITRATE>;
interrupt-parent = <&PLIC0>;
interrupts = <1>;
reg-shift = <2>; // regs are spaced on 32 bit boundary
@ -144,3 +144,5 @@
};
};
};
// delete ethernet device if disabled
/delete-node/ &eth; // DELETE_ETH

2
corev_apu/fpga/src/bootrom/src/main.c
View file

@ -9,7 +9,7 @@
int main()
{
init_uart(50000000, 115200);
init_uart(CLOCK_FREQUENCY, UART_BITRATE);
print_uart("Hello World!\r\n");
int res = gpt_find_boot_partition((uint8_t *)0x80000000UL, 2 * 16384);

14
corev_apu/fpga/src/nexys_video.svh Normal file
View file

@ -0,0 +1,14 @@
`define NEXYS_VIDEO
`define ARIANE_DATA_WIDTH 64
// Instantiate protocl checker
// `define PROTOCOL_CHECKER
// write-back cache
// `define WB_DCACHE
// write-through cache
`define WT_DCACHE
`define RAMB16

17
corev_apu/fpga/xilinx/xlnx_clk_gen/tcl/run.tcl
View file

@ -8,6 +8,22 @@ set_property board_part $boardName [current_project]
create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name $ipName
if {$::env(BOARD) eq "nexys_video"} {
set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} \
CONFIG.NUM_OUT_CLKS {5} \
CONFIG.CLKOUT2_USED {true} \
CONFIG.CLKOUT3_USED {true} \
CONFIG.CLKOUT4_USED {true} \
CONFIG.CLKOUT5_USED {true} \
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {25} \
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {125} \
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {125} \
CONFIG.CLKOUT3_REQUESTED_PHASE {90.000} \
CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {50} \
CONFIG.CLKOUT5_REQUESTED_OUT_FREQ {200} \
CONFIG.CLKIN1_JITTER_PS {50.0} \
] [get_ips $ipName]
} else {
set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000} \
CONFIG.NUM_OUT_CLKS {4} \
CONFIG.CLKOUT2_USED {true} \
@ -20,6 +36,7 @@ set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000} \
CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {50} \
CONFIG.CLKIN1_JITTER_PS {50.0} \
] [get_ips $ipName]
}
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]

137
corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_nexys_video.prj Normal file
View file

@ -0,0 +1,137 @@
<?xml version='1.0' encoding='UTF-8'?>
<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
<Project NoOfControllers="1" >
<ModuleName>xlnx_mig_7_ddr3</ModuleName>
<dci_inouts_inputs>1</dci_inouts_inputs>
<dci_inputs>1</dci_inputs>
<Debug_En>OFF</Debug_En>
<DataDepth_En>1024</DataDepth_En>
<LowPower_En>ON</LowPower_En>
<XADC_En>Enabled</XADC_En>
<TargetFPGA>xc7a200t-sbg484/-1</TargetFPGA>
<Version>4.1</Version>
<SystemClock>Single-Ended</SystemClock>
<ReferenceClock>No Buffer</ReferenceClock>
<SysResetPolarity>ACTIVE LOW</SysResetPolarity>
<BankSelectionFlag>FALSE</BankSelectionFlag>
<InternalVref>1</InternalVref>
<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
<dci_cascade>0</dci_cascade>
<Controller number="0" >
<MemoryDevice>DDR3_SDRAM/Components/MT41K256M16XX-125</MemoryDevice>
<TimePeriod>2500</TimePeriod>
<VccAuxIO>1.8V</VccAuxIO>
<PHYRatio>4:1</PHYRatio>
<InputClkFreq>100</InputClkFreq>
<UIExtraClocks>0</UIExtraClocks>
<MMCM_VCO>800</MMCM_VCO>
<MMCMClkOut0> 1.000</MMCMClkOut0>
<MMCMClkOut1>1</MMCMClkOut1>
<MMCMClkOut2>1</MMCMClkOut2>
<MMCMClkOut3>1</MMCMClkOut3>
<MMCMClkOut4>1</MMCMClkOut4>
<DataWidth>16</DataWidth>
<DeepMemory>1</DeepMemory>
<DataMask>1</DataMask>
<ECC>Disabled</ECC>
<Ordering>Normal</Ordering>
<BankMachineCnt>4</BankMachineCnt>
<CustomPart>FALSE</CustomPart>
<NewPartName></NewPartName>
<RowAddress>15</RowAddress>
<ColAddress>10</ColAddress>
<BankAddress>3</BankAddress>
<MemoryVoltage>1.5V</MemoryVoltage>
<UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
<PinSelection>
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="M2" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="L5" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="N5" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="N4" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="P2" SLEW="" name="ddr3_addr[13]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="P6" SLEW="" name="ddr3_addr[14]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="M5" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="M3" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="M1" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="L6" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="P1" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="N3" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="N2" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="M6" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="R1" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="L3" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="K6" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="L4" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="K3" SLEW="" name="ddr3_cas_n" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="P4" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="P5" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="J6" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="G3" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="F1" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="G2" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="F3" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="D2" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="C2" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="A1" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="E2" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="B1" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="H4" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="H5" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="J1" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="K1" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="H3" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="H2" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="J5" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="E3" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="B2" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="J2" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="D1" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="K2" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="E1" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="K4" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="J4" SLEW="" name="ddr3_ras_n" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="LVCMOS15" PADName="G1" SLEW="" name="ddr3_reset_n" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="L1" SLEW="" name="ddr3_we_n" IN_TERM="" />
</PinSelection>
<System_Clock>
<Pin PADName="R4(MRCC_P)" Bank="34" name="sys_clk_i" />
</System_Clock>
<System_Control>
<Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
<Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
<Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
</System_Control>
<TimingParameters>
<Parameters twtr="7.5" trrd="7.5" trefi="7.8" tfaw="40" trtp="7.5" tcke="5" trfc="260" trp="13.75" tras="35" trcd="13.75" />
</TimingParameters>
<mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
<mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
<mrCasLatency name="CAS Latency" >6</mrCasLatency>
<mrMode name="Mode" >Normal</mrMode>
<mrDllReset name="DLL Reset" >No</mrDllReset>
<mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
<emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
<emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/6</emrOutputDriveStrength>
<emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
<emrCSSelection name="Controller Chip Select Pin" >Disable</emrCSSelection>
<emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
<emrPosted name="Additive Latency (AL)" >0</emrPosted>
<emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
<emrDQS name="TDQS enable" >Enabled</emrDQS>
<emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
<mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
<mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>
<mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
<mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
<PortInterface>AXI</PortInterface>
<AXIParameters>
<C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
<C0_S_AXI_ADDR_WIDTH>29</C0_S_AXI_ADDR_WIDTH>
<C0_S_AXI_DATA_WIDTH>64</C0_S_AXI_DATA_WIDTH>
<C0_S_AXI_ID_WIDTH>5</C0_S_AXI_ID_WIDTH>
<C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
</AXIParameters>
</Controller>
</Project>

4
corev_apu/tb/ariane_soc_pkg.sv
View file

@ -44,7 +44,11 @@ package ariane_soc;
localparam logic[63:0] SPILength = 64'h800000;
localparam logic[63:0] EthernetLength = 64'h10000;
localparam logic[63:0] GPIOLength = 64'h1000;
`ifdef NEXYS_VIDEO
localparam logic[63:0] DRAMLength = 64'h20000000; // 512MByte of DDR on Nexys video board
`else
localparam logic[63:0] DRAMLength = 64'h40000000; // 1GByte of DDR (split between two chips on Genesys2)
`endif
localparam logic[63:0] SRAMLength = 64'h1800000; // 24 MByte of SRAM
// Instantiate AXI protocol checkers
localparam bit GenProtocolChecker = 1'b0;