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https://github.com/openhwgroup/cva6.git
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Merge pull request #167 from msfschaffner/master
Switch JTAG from PMOD to FTDI chip, update OpenPiton file list and OpenOCD cfg files.
This commit is contained in:
Florian Zaruba
GitHub
commit
5d3260196b
7 changed files with 101 additions and 33 deletions
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@ -6,6 +6,12 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
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## [Unreleased]
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### Added
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### Changed
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- Rerouted the JTAG from PMOD to second channel of FTDI 2232 chip on Genesys 2 board
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### 4.0.0
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### Added
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@ -131,9 +131,9 @@ src/debug/dmi_cdc.sv
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src/debug/dmi_jtag.sv
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src/debug/dm_sba.sv
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src/debug/dmi_jtag_tap.sv
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src/debug/debug_rom/debug_rom.sv
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openpiton/ariane_verilog_wrap.sv
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openpiton/serpent_peripherals.sv
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openpiton/debug_rom/debug_rom.sv
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bootrom/bootrom.sv
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src/plic/plic.sv
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src/plic/plic_claim_complete_tracker.sv
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32
README.md
32
README.md
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@ -157,21 +157,25 @@ This will produce a bitstream file and memory configuration file (in `fpga/work-
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### Debugging
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You can debug (and program) the FPGA using [OpenOCD](http://openocd.org/doc/html/Architecture-and-Core-Commands.html). We provide two example scripts for OpenOCD, both to be used with Olimex Debug adapter. The JTAG port is mapped to PMOD `JC` on the Genesys 2 board. You will need to connect the following wires to your debug adapter:
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You can debug (and program) the FPGA using [OpenOCD](http://openocd.org/doc/html/Architecture-and-Core-Commands.html). We provide two example scripts for OpenOCD below.
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To get started, connect the micro USB port that is labeled with JTAG to your machine. This port is attached to the FTDI 2232 USB-to-serial chip on the Genesys 2 board, and is usually used to access the native JTAG interface of the Kintex-7 FPGA (e.g. to program the device using Vivado). However, the FTDI chip also exposes a second serial link that is routed to GPIO pins on the FPGA, and we leverage this to wire up the JTAG from the RISC-V debug module.
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| Pin | Nr. |
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|----------|-----|
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| `tck` | JC1 |
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| `tdi` | JC2 |
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| `tdo` | JC3 |
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| `tms` | JC4 |
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| `trst_n` | JC7 |
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>If you are on an Ubuntu based system you need to add the following udev rule to `/etc/udev/rules.d/99-ftdi.rules`
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>```
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> SUBSYSTEM=="usb", ACTION=="add", ATTRS{idProduct}=="6010", ATTRS{idVendor}=="0403", MODE="664", GROUP="plugdev"
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>```
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Once attached to your system, the FTDI chip should be listed when you type `lsusb`
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```
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$ openocd -f fpga/ariane_tiny.cfg
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Bus 005 Device 019: ID 0403:6010 Future Technology Devices International, Ltd FT2232C/D/H Dual UART/FIFO IC
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```
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If this is the case, you can go on and start openocd with the `fpga/ariane.cfg` configuration file:
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```
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$ openocd -f fpga/ariane.cfg
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Open On-Chip Debugger 0.10.0+dev-00195-g933cb87 (2018-09-14-19:32)
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Licensed under GNU GPL v2
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For bug reports, read
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@ -180,7 +184,7 @@ adapter speed: 1000 kHz
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Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
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Info : clock speed 1000 kHz
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Info : TAP riscv.cpu does not have IDCODE
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Info : datacount=2 progbufsize=12
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Info : datacount=2 progbufsize=8
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Info : Examined RISC-V core; found 1 harts
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Info : hart 0: XLEN=64, misa=0x8000000000141105
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Info : Listening on port 3333 for gdb connections
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@ -219,12 +223,6 @@ You can read or write device memory by using:
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(gdb) set $pc = 0x1000
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```
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If you are on an Ubuntu based system you need to add the following udev rule to `/etc/udev/rules.d/olimex-arm-usb-tiny-h.rules`
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>```
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> SUBSYSTEM=="usb", ACTION=="add", ATTRS{idProduct}=="002a", ATTRS{idVendor}=="15ba", MODE="664", GROUP="plugdev"
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>```
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### Preliminary Support for OpenPiton Cache System
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Ariane has preliminary support for the OpenPiton distributed cache system from Princeton University. To this end, a different L1 cache subsystem (`src/cache_subsystem/serpent_cache_subsystem.sv`) has been developed that follows a write-through protocol and that has support for cache invalidations and atomics.
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@ -1,13 +1,24 @@
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adapter_khz 1000
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interface ftdi
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# ftdi_device_desc "Olimex Ltd. ARM-USB-OCD-H JTAG+RS232"
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ftdi_vid_pid 0x15ba 0x002b
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ftdi_vid_pid 0x0403 0x6010
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ftdi_layout_init 0x0808 0x0a1b
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ftdi_layout_signal nSRST -oe 0x0200
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ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
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ftdi_layout_signal LED -data 0x0800
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# Channel 1 is taken by Xilinx JTAG
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ftdi_channel 0
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# links:
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# http://openocd.org/doc-release/html/Debug-Adapter-Configuration.html
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#
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# Bit MPSSE FT2232 JTAG Type Description
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# Bit0 TCK ADBUS0 TCK Out Clock Signal Output
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# Bit1 TDI ADBUS1 TDI Out Serial Data Out
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# Bit2 TDO ADBUS2 TDO In Serial Data In
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# Bit3 TMS ADBUS3 TMS Out Select Signal Out
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# Bit4 GPIOL0 ADBUS4 nTRST In/Out General Purpose I/O
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# this corresponds to the following in/out layout, with TMS initially set to 1
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ftdi_layout_init 0x0018 0x001b
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# we only have to specify nTRST, the others are assigned correctly by default
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ftdi_layout_signal nTRST -ndata 0x0010
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set _CHIPNAME riscv
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jtag newtap $_CHIPNAME cpu -irlen 5
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30
fpga/ariane_pmod.cfg
Normal file
30
fpga/ariane_pmod.cfg
Normal file
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@ -0,0 +1,30 @@
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adapter_khz 1000
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interface ftdi
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# ftdi_device_desc "Olimex Ltd. ARM-USB-OCD-H JTAG+RS232"
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ftdi_vid_pid 0x15ba 0x002b
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ftdi_layout_init 0x0808 0x0a1b
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ftdi_layout_signal nSRST -oe 0x0200
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ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
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ftdi_layout_signal LED -data 0x0800
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set _CHIPNAME riscv
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jtag newtap $_CHIPNAME cpu -irlen 5
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set _TARGETNAME $_CHIPNAME.cpu
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# select the HART to debug with the coreid switch
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target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0
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gdb_report_data_abort enable
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gdb_report_register_access_error enable
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riscv set_reset_timeout_sec 120
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riscv set_command_timeout_sec 120
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# prefer to use sba for system bus access
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riscv set_prefer_sba off
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init
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halt
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echo "Ready for Remote Connections"
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@ -13,7 +13,8 @@ set _CHIPNAME riscv
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jtag newtap $_CHIPNAME cpu -irlen 5
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME riscv -chain-position $_TARGETNAME
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# select the HART to debug with the coreid switch
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target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0
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gdb_report_data_abort enable
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gdb_report_register_access_error enable
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@ -1,19 +1,27 @@
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\## Buttons
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## Buttons
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set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS33} [get_ports cpu_resetn]
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## PMOD Header JC
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set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS33} [get_ports tck]
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set_property -dict {PACKAGE_PIN AJ27 IOSTANDARD LVCMOS33} [get_ports tdi]
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set_property -dict {PACKAGE_PIN AH30 IOSTANDARD LVCMOS33} [get_ports tdo]
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set_property -dict {PACKAGE_PIN AK29 IOSTANDARD LVCMOS33} [get_ports tms]
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set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS33} [get_ports trst_n]
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# set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS33} [get_ports tck]
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# set_property -dict {PACKAGE_PIN AJ27 IOSTANDARD LVCMOS33} [get_ports tdi]
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# set_property -dict {PACKAGE_PIN AH30 IOSTANDARD LVCMOS33} [get_ports tdo]
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# set_property -dict {PACKAGE_PIN AK29 IOSTANDARD LVCMOS33} [get_ports tms]
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# set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS33} [get_ports trst_n]
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# accept sub-optimal placement
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# set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets tck_IBUF]
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## To use FTDI FT2232 JTAG
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set_property -dict { PACKAGE_PIN Y29 IOSTANDARD LVCMOS33 } [get_ports { trst_n }];
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set_property -dict { PACKAGE_PIN AD27 IOSTANDARD LVCMOS33 } [get_ports { tck }];
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set_property -dict { PACKAGE_PIN W27 IOSTANDARD LVCMOS33 } [get_ports { tdi }];
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set_property -dict { PACKAGE_PIN W28 IOSTANDARD LVCMOS33 } [get_ports { tdo }];
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set_property -dict { PACKAGE_PIN W29 IOSTANDARD LVCMOS33 } [get_ports { tms }];
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## UART
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set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS33} [get_ports tx]
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set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports rx]
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# accept sub-optimal placement
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets tck_IBUF]
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## LEDs
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set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS33} [get_ports {led[0]}]
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@ -69,6 +77,7 @@ create_clock -period 40.000 -name eth_rxck_virt
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# conservatively assuming +/- 2ns skew of rxd/rxctl
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create_clock -period 40.000 -name eth_rxck -waveform {2.000 22.000} [get_ports eth_rxck]
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# Input constraints
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set_input_delay -clock [get_clocks eth_rxck_virt] -min -add_delay 0.000 [get_ports {eth_rxd[*]}]
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set_input_delay -clock [get_clocks eth_rxck_virt] -max -add_delay 4.000 [get_ports {eth_rxd[*]}]
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@ -92,3 +101,16 @@ set_property -dict {PACKAGE_PIN R29 IOSTANDARD LVCMOS33} [get_ports spi_mosi]
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# Genesys 2 has a quad SPI flash
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set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
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## JTAG
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# minimize routing delay
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set_max_delay -to [get_ports { td } ] 5
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set_max_delay -from [get_ports { tms } ] 5
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set_max_delay -from [get_ports { trst_n } ] 5
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# reset signal
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set_false_path -from [get_ports { trst_n } ]
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# constrain clock domain crossing
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set_false_path -from [get_clocks tck] -to [get_clocks clk_out1]
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set_max_delay -from [get_clocks tck] -to [get_clocks clk_out1] 5
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