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Co-authored-by: Frikha Mohamed Aziz <mohamed-aziz.frikha@thalesgroup.com>
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Mohamed Aziz Frikha
GitHub
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@ -199,8 +199,10 @@ The ``mstatus`` register keeps track of and controls the hart’s current operat
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| 16:15 | XS | Extension state | read-only | The XS field is used to reduce the cost of context save and restore by setting and tracking the current state of the user\-mode extensions\. The XS field encodes the status of the additional user\-mode extensions and associated state\. This field can be checked by a context switch routine to quickly determine whether a state save or restore is required\. If a save or restore is required, additional instructions and CSRs are typically required to effect and optimize the process\. // ``Enumerated Values``( "Off" :0 ) ( "Initial" :1 ) ( "Clean" :2 ) ( "Dirty" :3 ) |
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| 14:13 | FS | Floating-point unit state | read-write | The FS field is used to reduce the cost of context save and restore by setting and tracking the current state of the floating\-point unit\. The FS field encodes the status of the floating\-point unit state, including the floating\-point registers ``f0–f31`` and the CSRs ``fcsr``, ``frm``, and ``fflags``\. This field can be checked by a context switch routine to quickly determine whether a state save or restore is required\. If a save or restore is required, additional instructions and CSRs are typically required to effect and optimize the process\. // ``Enumerated Values``( "Off" :0 ) ( "Initial" :1 ) ( "Clean" :2 ) ( "Dirty" :3 ) |
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| 12:11 | MPP | Machine mode prior privilege | read-write | Holds the previous privilege mode for machine mode\.|
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| 10:9 | VS | Vector extension state | read-only | V extension is not supported VS=0\.|
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| 8 | SPP | Supervisor mode prior privilege | read-write | Holds the previous privilege mode for supervisor mode\.|
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| 7 | MPIE | Machine mode prior interrupt enable | read-write | Indicates whether machine interrupts were enabled prior to trapping into machine mode\.|
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| 6 | UBE | User breakpoint enable | read-write | UBE controls whether explicit load and store memory accesses made from U\-mode are little\-endian \(UBE=0\) or big\-endian \(UBE=1\)\.|
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| 5 | SPIE | Supervisor mode prior interrupt enable | read-write | Indicates whether supervisor interrupts were enabled prior to trapping into supervisor mode\.|
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| 4 | WPRI2 | Reserved writes preserve values, reads ignore value | read-write | Reserved Writes Preserve Values, Reads Ignore Value|
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| 3 | MIE | Machine mode interrupt enable | read-write | Global interrupt\-enable bit for Machine mode\.|
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@ -652,6 +652,11 @@ The ``mstatus`` register keeps track of and controls the hart’s current operat
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- Machine mode prior privilege
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- read-write
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- Holds the previous privilege mode for machine mode\.
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* - 10:9
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- VS
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- Vector extension state
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- read-only
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- V extension is not supported VS=0\.
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* - 8
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- SPP
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- Supervisor mode prior privilege
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@ -662,6 +667,11 @@ The ``mstatus`` register keeps track of and controls the hart’s current operat
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- Machine mode prior interrupt enable
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- read-write
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- Indicates whether machine interrupts were enabled prior to trapping into machine mode\.
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* - 6
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- UBE
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- User breakpoint enable
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- read-write
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- UBE controls whether explicit load and store memory accesses made from U\-mode are little\-endian \(UBE=0\) or big\-endian \(UBE=1\)\.
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* - 5
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- SPIE
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- Supervisor mode prior interrupt enable
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@ -1352,6 +1352,23 @@ This field can be checked by a context switch routine to quickly determine wheth
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<ipxact:bitWidth>2</ipxact:bitWidth>
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<ipxact:access>read-write</ipxact:access>
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</ipxact:field>
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<ipxact:field>
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<ipxact:name>VS</ipxact:name>
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<ipxact:displayName>Vector extension State</ipxact:displayName>
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<ipxact:description>V extension is not supported VS=0.</ipxact:description>
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<ipxact:bitOffset>9</ipxact:bitOffset>
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<ipxact:resets>
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<ipxact:reset>
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<ipxact:value>0x0</ipxact:value>
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<ipxact:mask>0x3</ipxact:mask>
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</ipxact:reset>
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</ipxact:resets>
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<ipxact:bitWidth>2</ipxact:bitWidth>
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<ipxact:access>read-only</ipxact:access>
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<ipxact:vendorExtensions>
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<RISCV_behavior>WARL</RISCV_behavior>
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</ipxact:vendorExtensions>
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</ipxact:field>
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<ipxact:field>
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<ipxact:name>SPP</ipxact:name>
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<ipxact:displayName>Supervisor mode Prior Privilege</ipxact:displayName>
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@ -1380,6 +1397,23 @@ This field can be checked by a context switch routine to quickly determine wheth
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<ipxact:bitWidth>1</ipxact:bitWidth>
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<ipxact:access>read-write</ipxact:access>
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</ipxact:field>
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<ipxact:field>
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<ipxact:name>UBE</ipxact:name>
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<ipxact:displayName>User Breakpoint Enable</ipxact:displayName>
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<ipxact:description>UBE controls whether explicit load and store memory accesses made from U-mode are little-endian (UBE=0) or big-endian (UBE=1).</ipxact:description>
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<ipxact:bitOffset>6</ipxact:bitOffset>
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<ipxact:resets>
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<ipxact:reset>
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<ipxact:value>0x0</ipxact:value>
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<ipxact:mask>0x1</ipxact:mask>
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</ipxact:reset>
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</ipxact:resets>
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<ipxact:bitWidth>1</ipxact:bitWidth>
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<ipxact:access>read-write</ipxact:access>
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<ipxact:vendorExtensions>
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<RISCV_behavior>WARL</RISCV_behavior>
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</ipxact:vendorExtensions>
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</ipxact:field>
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<ipxact:field>
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<ipxact:name>SPIE</ipxact:name>
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<ipxact:displayName>Supervisor mode Prior Interrupt Enable</ipxact:displayName>
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@ -958,6 +958,18 @@ component:
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mask: '0x3'
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bitWidth: '2'
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access: read-write
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- name: VS
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displayName: Vector extension State
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description: V extension is not supported VS=0.
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bitOffset: '9'
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resets:
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reset:
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value: '0x0'
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mask: '0x3'
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bitWidth: '2'
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access: read-only
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vendorExtensions:
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RISCV_behavior: WARL
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- name: SPP
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displayName: Supervisor mode Prior Privilege
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description: Holds the previous privilege mode for supervisor mode.
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@ -978,6 +990,18 @@ component:
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mask: '0x1'
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bitWidth: '1'
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access: read-write
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- name: UBE
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displayName: User Breakpoint Enable
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description: UBE controls whether explicit load and store memory accesses made from U-mode are little-endian (UBE=0) or big-endian (UBE=1).
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bitOffset: '6'
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resets:
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reset:
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value: '0x0'
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mask: '0x1'
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bitWidth: '1'
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access: read-write
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vendorExtensions:
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RISCV_behavior: WARL
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- name: SPIE
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displayName: Supervisor mode Prior Interrupt Enable
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description: Indicates whether supervisor interrupts were enabled prior to trapping into supervisor mode.
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