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🐛 Fix debug rvalid and also halt if not fetchen
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97b8b12a42
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2 changed files with 8 additions and 6 deletions
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@ -574,6 +574,7 @@ module ariane
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.commit_ack_i ( commit_ack ),
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.ex_i ( ex_commit ),
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.halt_o ( halt_debug_ctrl ),
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.fetch_enable_i ( fetch_enable ),
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.debug_pc_o ( pc_debug_pcgen ),
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.debug_set_pc_o ( set_pc_debug ),
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@ -27,6 +27,7 @@ module debug_unit (
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input logic commit_ack_i,
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input exception ex_i, // instruction caused an exception
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output logic halt_o, // halt the hart
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input logic fetch_enable_i, // fetch enable signal
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// GPR interface
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output logic debug_gpr_req_o,
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output logic [4:0] debug_gpr_addr_o,
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@ -98,7 +99,7 @@ module debug_unit (
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always_comb begin : debug_ctrl
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debug_gnt_o = 1'b0;
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rdata_n = 'b0;
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rvalid_n = 1'b0;
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rvalid_n = debug_req_i;
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halt_req = 1'b0;
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resume_req = 1'b0;
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@ -269,7 +270,7 @@ module debug_unit (
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HALT_REQ: begin
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halt_o = 1'b1;
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// we've got a valid instruction in the commit stage so we can proceed to the halted state
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if (commit_instr_i.valid) begin
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if (commit_instr_i.valid || !fetch_enable_i) begin
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NS = HALTED;
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end
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end
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@ -335,10 +336,10 @@ module debug_unit (
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// check that no registers are accessed when we are not in debug mode
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assert property (
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@(posedge clk_i) (debug_req_i) |-> ((debug_halted_o == 1'b1) ||
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((debug_addr_i[14] != 1'b1) &&
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(debug_addr_i[13:7] != 5'b0_1001) &&
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(debug_addr_i[13:7] != 5'b0_1000)) ) )
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else $warning("Trying to access internal debug registers while core is not stalled");
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((debug_addr_i[14] != 1'b1) &&
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(debug_addr_i[13:7] != 5'b0_1001) &&
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(debug_addr_i[13:7] != 5'b0_1000)) ) )
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else $warning("Trying to access internal debug registers while core is not halted");
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// check that all accesses are word-aligned
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assert property (
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