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🐛 Fix prediction only fetching half an instr
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2 changed files with 4 additions and 2 deletions
2
Makefile
2
Makefile
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@ -43,7 +43,7 @@ riscv-tests = rv64ui-p-add rv64ui-p-addi rv64ui-p-slli rv64ui-p-addiw rv64ui-p-a
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rv64mi-p-csr rv64mi-p-mcsr rv64mi-p-illegal \
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rv64mi-p-ma_addr rv64mi-p-ma_fetch rv64mi-p-sbreak rv64mi-p-scall \
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rv64si-p-csr rv64si-p-ma_fetch rv64si-p-scall rv64si-p-wfi rv64si-p-sbreak \
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rv64si-p-dirty
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rv64si-p-dirty rv64uc-p-rvc
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riscv-test = rv64ui-p-add
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@ -91,7 +91,9 @@ module pcgen (
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// 1. Predict taken
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// -------------------------------
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// only predict if the IF stage is ready, otherwise we might take the predicted PC away which will end in a endless loop
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if (if_ready_i && branch_predict_btb.valid && branch_predict_btb.predict_taken) begin
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// also check if we fetched on a half word (npc_q[1] == 1), it might be the case that we need the next 16 byte of the following instruction
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// prediction could potentially prevent us from getting them
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if (if_ready_i && branch_predict_btb.valid && branch_predict_btb.predict_taken && !npc_q[1]) begin
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npc_n = branch_predict_btb.predict_address;
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end
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// -------------------------------
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