@ -18,9 +18,9 @@ code can access all CSRs at lower privilege levels.
endif::[]
[[misa]]
==== Machine ISA Register `misa`
==== Machine ISA (`misa`) Register
The `misa` CSR is a *WARL* read-write register reporting the ISA supported by the hart.
The `misa` CSR is a *WARL* read-write register reporting the ISA supported by the hart.
ifeval::[{ohg-config} != CV32A65X]
This register must be readable in any implementation, but a value of zero can be returned to indicate the `misa` register has not been implemented, requiring that CPU capabilities be determined through a separate non-standard mechanism.
endif::[]
@ -68,7 +68,7 @@ knowing the register width (MXLEN) of the hart. The base width is
given by __MXLEN=2^MXL+4^__.
The base width can also be found if `misa` is zero, by placing the
immediate 4 in a register then shifting the register left by 31 bits at
immediate 4 in a register, then shifting the register left by 31 bits at
a time. If zero after one shift, then the hart is RV32. If zero after
two shifts, then the hart is RV64, else RV128.
====
@ -97,7 +97,9 @@ with a single bit per letter of the alphabet (bit 0 encodes presence of
extension "A" , bit 1 encodes presence of extension "B", through to
bit 25 which encodes "Z"). The "I" bit will be set for RV32I, RV64I,
and RV128I base ISAs, and the "E" bit will be set for RV32E and RV64E.
In CVA6, the Extensions field is not writeable, the presence of standard extensions corresponds to the hardware reset value and cannot be modified by writing in the register.
In CVA6, the Extensions field is not writeable, the presence of standard
extensions corresponds to the hardware reset value and cannot be modified
by writing in the register.
endif::[]
@ -173,7 +175,7 @@ K +
L +
M +
N +
O +
O +
P +
Q +
R +
@ -277,7 +279,7 @@ when a feature is not implemented, the corresponding opcodes and CSRs become
reserved, not necessarily illegal.
endif::[]
==== Machine Vendor ID Register `mvendorid`
==== Machine Vendor ID (`mvendorid`) Register
ifeval::[{ohg-config} != CV32A65X]
The `mvendorid` CSR is a 32-bit read-only register providing the JEDEC
@ -289,7 +291,9 @@ endif::[]
ifeval::[{ohg-config} == CV32A65X]
[CVA6] The `mvendorid` CSR is a 32-bit read-only register providing the JEDEC
manufacturer ID of the provider of the core. In CVA6, `mvendorid` is implemented and returns the commercial implementation id supplied to OpenHW Group organization, 0x602.
manufacturer ID of the provider of the core.
In CVA6, `mvendorid` is implemented and returns the commercial implementation
id supplied to OpenHW Group organization, 0x602.
endif::[]
//.Vendor ID register (`mvendorid`)
@ -325,7 +329,7 @@ ID with JEDEC has a one-time cost of $500.
====
endif::[]
==== Machine Architecture ID Register `marchid`
==== Machine Architecture ID (`marchid`) Register
ifeval::[{ohg-config} != CV32A65X]
The `marchid` CSR is an MXLEN-bit read-only register encoding the base
@ -338,10 +342,12 @@ endif::[]
ifeval::[{ohg-config} == CV32A65X]
[CVA6] The `marchid` CSR is an MXLEN-bit read-only register encoding the base
microarchitecture of the hart. In CVA6, `marchid` is implemented and returns the base microarchitecture of the hart supplied to CVA6, 0x3.
microarchitecture of the hart.
In CVA6, `marchid` is implemented and returns the base microarchitecture
of the hart supplied to CVA6, 0x3.
endif::[]
.Machine Architecture ID register (`marchid`)
.Machine Architecture ID (`marchid`) register
include::images/bytefield/marchid.adoc[]
ifeval::[{ohg-config} != CV32A65X]
@ -375,7 +381,7 @@ variants of a design.
====
endif::[]
==== Machine Implementation ID Register `mimpid`
==== Machine Implementation ID (`mimpid`) Register
ifeval::[{ohg-config} != CV32A65X]
The `mimpid` CSR provides a unique encoding of the version of the
@ -394,7 +400,7 @@ The Implementation value should reflect the design of the RISC-V
processor itself and not any surrounding system.
endif::[]
.Machine Implementation ID register (`mimpid`)
.Machine Implementation ID (`mimpid`) register
include::images/bytefield/mimpid.adoc[]
ifeval::[{note} == true]
@ -409,7 +415,7 @@ boundaries to ease human readability.
====
endif::[]
==== Hart ID Register `mhartid`
==== Hart ID (`mhartid`) Register
ifeval::[{ohg-config} != CV32A65X]
The `mhartid` CSR is an MXLEN-bit read-only register containing the
@ -427,7 +433,7 @@ readable. In {ohg-config}-based system, only one hart is implemented.
Hart ID is zero.
endif::[]
.Hart ID register (`mhartid`)
.Hart ID (`mhartid`) register
include::images/bytefield/mhartid.adoc[]
ifeval::[{note} == true]
@ -441,7 +447,7 @@ of the largest hart ID used in a system.
====
endif::[]
==== Machine Status Registers (`mstatus` and `mstatush`)
==== Machine Status (`mstatus` and `mstatush`) Registers
ifeval::[{ohg-config} != CV32A65X]
The `mstatus` register is an MXLEN-bit read/write register formatted as
@ -459,14 +465,74 @@ keeps track of and controls the hart’s current operating state.
endif::[]
[[mstatusreg-rv32]]
.Machine-mode status register (`mstatus`) for RV32
include::images/bytefield/mstatusreg-rv32.adoc[]
.Machine-mode status (`mstatus`) register for RV32
[wavedrom, ,svg]
....
{reg: [
{bits: 1, name: 'WPRI'},
{bits: 1, name: 'SIE'},
{bits: 1, name: 'WPRI'},
{bits: 1, name: 'MIE'},
{bits: 1, name: 'WPRI'},
{bits: 1, name: 'SPIE'},
{bits: 1, name: 'UBE'},
{bits: 1, name: 'MPIE'},
{bits: 1, name: 'SPP'},
{bits: 2, name: 'VS[1:0]'},
{bits: 2, name: 'MPP[1:0]'},
{bits: 2, name: 'FS[1:0]'},
{bits: 2, name: 'XS[1:0]'},
{bits: 1, name: 'MPRV'},
{bits: 1, name: 'SUM'},
{bits: 1, name: 'MXR'},
{bits: 1, name: 'TVM'},
{bits: 1, name: 'TW'},
{bits: 1, name: 'TSR'},
{bits: 1, name: 'SPELP'},
{bits: 7, name: 'WPRI'},
{bits: 1, name: 'SD'},
], config:{lanes: 2, hspace:1024}}
....
ifeval::[{ohg-config} != CV32A65X]
include::images/bytefield/mstatusreg.adoc[]
[[mstatusreg]]
.Machine-mode status register (`mstatus`) for RV64
include::images/bytefield/mstatusreg2.adoc[]
.Machine-mode status (`mstatus`) register for RV64
[wavedrom, ,svg]
....
{reg: [
{bits: 1, name: 'WPRI'},
{bits: 1, name: 'SIE'},
{bits: 1, name: 'WPRI'},
{bits: 1, name: 'MIE'},
{bits: 1, name: 'WPRI'},
{bits: 1, name: 'SPIE'},
{bits: 1, name: 'UBE'},
{bits: 1, name: 'MPIE'},
{bits: 1, name: 'SPP'},
{bits: 2, name: 'VS[1:0]'},
{bits: 2, name: 'MPP[1:0]'},
{bits: 2, name: 'FS[1:0]'},
{bits: 2, name: 'XS[1:0]'},
{bits: 1, name: 'MPRV'},
{bits: 1, name: 'SUM'},
{bits: 1, name: 'MXR'},
{bits: 1, name: 'TVM'},
{bits: 1, name: 'TW'},
{bits: 1, name: 'TSR'},
{bits: 1, name: 'SPELP'},
{bits: 8, name: 'WPRI'},
{bits: 2, name: 'UXL[1:0]'},
{bits: 2, name: 'SXL[1:0]'},
{bits: 1, name: 'SBE'},
{bits: 1, name: 'MBE'},
{bits: 1, name: 'GVA'},
{bits: 1, name: 'MPV'},
{bits: 1, name: 'WPRI'},
{bits: 1, name: 'MPELP'},
{bits: 21, name: 'WPRI'},
{bits: 1, name: 'SD'},
], config:{lanes: 4, hspace:1024}}
....
endif::[]
ifeval::[{ohg-config} != CV32A65X]
@ -480,8 +546,16 @@ shown in <<mstatushreg>>.
endif::[]
[[mstatushreg]]
.Additional machine-mode status register (`mstatush`) for RV32.
include::images/bytefield/mstatushreg.adoc[]
.Additional machine-mode status (`mstatush`) register for RV32.
[wavedrom, ,svg]
....
{reg: [
{bits: 4, name: 'WPRI'},
{bits: 1, name: 'SBE'},
{bits: 1, name: 'MBE'},
{bits: 26, name: 'WPRI'},
], config:{lanes: 1, hspace:1024}}
....
[[privstack]]
===== Privilege and Global Interrupt-Enable Stack in `mstatus` register
@ -618,14 +692,6 @@ ifeval::[{RVS} == false]
and UPP are read-only 0.
endif::[]
ifeval::[{note} == true]
[NOTE]
====
M-mode software can determine whether a privilege mode is implemented by
writing that mode to MPP then reading it back.
====
endif::[]
[[xlen-control]]
===== Base ISA Control in `mstatus` Register
@ -727,7 +793,7 @@ whether access-fault exceptions are raised due to PMAs or PMP.
endif::[]
ifeval::[{RVS} == false]
[{ohg-config}] As U-Mode is not implemented, MPRV is read-only 0.
[{ohg-config}] As U-Mode is not implemented, the MPRV (Modify PRiVilege) bit is read-only 0.
Loads and stores behave as normal, using the translation and protection
mechanisms of the current privilege mode.
@ -741,11 +807,11 @@ The MBE, SBE, and UBE bits in `mstatus` and `mstatush` are *WARL* fields that
control the endianness of memory accesses other than instruction
fetches. Instruction fetches are always little-endian.
ifeval::[{RVS} == true]
MBE controls whether non-instruction-fetch memory accesses made from
M-mode (assuming `mstatus`.MPRV=0) are little-endian (MBE=0) or
big-endian (MBE=1).
ifeval::[{RVS} == true]
If S-mode is not supported, SBE is read-only 0. Otherwise, SBE controls
whether explicit load and store memory accesses made from S-mode are
little-endian (SBE=0) or big-endian (SBE=1).
@ -778,10 +844,6 @@ read-only copy of either MBE or SBE.
endif::[]
ifeval::[{RVS} == false]
MBE controls whether non-instruction-fetch memory accesses made from
M-mode (assuming `mstatus`.MPRV=0) are little-endian (MBE=0) or
big-endian (MBE=1).
[{ohg-config}]
It is always little-endian in M-Mode, the MBE is read-only zero.
@ -904,14 +966,6 @@ TW is read-only 0 because there are no modes less privileged
than M.
endif::[]
ifeval::[{note} == true]
[NOTE]
====
Trapping the WFI instruction can trigger a world switch to another guest
OS, rather than wastefully idling in the current guest.
====
endif::[]
ifeval::[{RVS} == true]
The TSR (Trap SRET) bit is a *WARL* field that supports intercepting the
supervisor exception return instruction, SRET. When TSR=1, attempts to
@ -1169,7 +1223,7 @@ alter its contents causes VS to transition to Dirty.
endif::[]
ifeval::[{ohg-config} != CV32A65X]
[{ohg-config}] <<fsxsstates>> shows all the possible state
<<fsxsstates>> shows all the possible state
transitions for the FS, VS, or XS status bits. Note that the standard
floating-point and vector extensions do not support user-mode
unconfigure or disable/enable instructions.
@ -1344,7 +1398,18 @@ interrupts, unless the interrupt results in a user-level context swap.
If bit FIOM (Fence of I/O implies Memory) is set to one in `menvcfg`,
FENCE instructions executed in modes less privileged than M are modified
@ -2549,25 +2626,39 @@ A/D bits need be set, hence Svade is implemented when ADUE=0.
If the Smcdeleg extension is implemented, the CDE (Counter Delegation Enable) bit controls whether Zicntr and Zihpm counters can be delegated to S-mode. When CDE=1, the Smcdeleg extension is enabled, see <<smcdeleg>>. When CDE=0, the Smcdeleg and Ssccfg extensions appear to be not implemented. If Smcdeleg is not implemented, CDE is read-only zero.
The definition of the STCE field will be furnished by the forthcoming
Sstc extension. Its allocation within `menvcfg` may change prior to the
ratification of that extension.
The definition of the STCE field is furnished by the Sstc extension.
The definition of the CBZE field will be furnished by the forthcoming
Zicboz extension. Its allocation within `menvcfg` may change prior to
the ratification of that extension.
The definition of the CBZE field is furnished by the Zicboz extension.
The definitions of the CBCFE and CBIE fields will be furnished by the
forthcoming Zicbom extension. Their allocations within `menvcfg` may
change prior to the ratification of that extension.
The definitions of the CBCFE and CBIE fields are furnished by the Zicbom extension.
The definition of the PMM field will be furnished by the forthcoming
Smnpm extension. Its allocation within `menvcfg` may change prior to the
ratification of that extension.
The Zicfilp extension adds the `LPE` field in `menvcfg`. When the `LPE` field is
set to 1 and S-mode is implemented, the Zicfilp extension is enabled in S-mode.
If `LPE` field is set to 1 and S-mode is not implemented, the Zicfilp extension
is enabled in U-mode. When the `LPE` field is 0, the Zicfilp extension is not
enabled in S-mode, and the following rules apply to S-mode. If the `LPE` field
is 0 and S-mode is not implemented, then the same rules apply to U-mode.
* The hart does not update the `ELP` state; it remains as `NO_LP_EXPECTED`.
* The `LPAD` instruction operates as a no-op.
The Zicfiss extension adds the `SSE` field to `menvcfg`. When the `SSE` field is
set to 1 the Zicfiss extension is activated in S-mode. When `SSE` field is 0,
the following rules apply to privilege modes that are less than M:
* 32-bit Zicfiss instructions will revert to their behavior as defined by Zimop.
* 16-bit Zicfiss instructions will revert to their behavior as defined by Zcmop.
* The `pte.xwr=010b` encoding in VS/S-stage page tables becomes reserved.
* The `henvcfg.SSE` and `senvcfg.SSE` fields will read as zero and are read-only.
* `SSAMOSWAP.W/D` raises an illegal-instruction exception.
When XLEN=32, `menvcfgh` is a 32-bit read/write register
that aliases bits 63:32 of `menvcfg`.
Register `menvcfgh` does not exist when XLEN=64.
The `menvcfgh` register does not exist when XLEN=64.
If U-mode is not supported, then registers `menvcfg` and `menvcfgh` do
André Sintzoff
GitHub