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Michael Schaffner 2019-04-25 18:59:27 +02:00 • committed by Florian Zaruba
parent 3a9d4e0f2c
commit 720910dad0
6 changed files with 14 additions and 22 deletions
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6
include/ariane_pkg.sv
View file

@ -101,7 +101,7 @@ package ariane_pkg;
function automatic logic is_inside_nonidempotent_regions (ariane_cfg_t Cfg, logic[63:0] address);
logic[NrMaxRules-1:0] pass;
pass = '0;
for (int unsigned k=0; k<Cfg.NrNonIdempotentRules; k++) begin
for (int unsigned k = 0; k < Cfg.NrNonIdempotentRules; k++) begin
pass[k] = range_check(Cfg.NonIdempotentAddrBase[k], Cfg.NonIdempotentLength[k], address);
end
return |pass;
@ -111,7 +111,7 @@ package ariane_pkg;
// if we don't specify any region we assume everything is accessible
logic[NrMaxRules-1:0] pass;
pass = '0;
for (int unsigned k=0; k<Cfg.NrExecuteRegionRules; k++) begin
for (int unsigned k = 0; k < Cfg.NrExecuteRegionRules; k++) begin
pass[k] = range_check(Cfg.ExecuteRegionAddrBase[k], Cfg.ExecuteRegionLength[k], address);
end
return |pass;
@ -120,7 +120,7 @@ package ariane_pkg;
function automatic logic is_inside_cacheable_regions (ariane_cfg_t Cfg, logic[63:0] address);
automatic logic[NrMaxRules-1:0] pass;
pass = '0;
for (int unsigned k=0; k<Cfg.NrCachedRegionRules; k++) begin
for (int unsigned k = 0; k < Cfg.NrCachedRegionRules; k++) begin
pass[k] = range_check(Cfg.CachedRegionAddrBase[k], Cfg.CachedRegionLength[k], address);
end
return |pass;

6
openpiton/ariane_verilog_wrap.sv
View file

@ -176,10 +176,10 @@ module ariane_verilog_wrap #(
CachedRegionAddrBase: CachedRegionAddrBase,
CachedRegionLength: CachedRegionLength,
// cache config
Axi64BitCompliant: 1'b0,
SwapEndianess: SwapEndianess,
Axi64BitCompliant: 1'b0,
SwapEndianess: SwapEndianess,
// debug
DmBaseAddress: DmBaseAddress
DmBaseAddress: DmBaseAddress
};
ariane #(

3
src/ariane.sv
View file

@ -15,8 +15,6 @@
import ariane_pkg::*;
module ariane #(
parameter int unsigned AxiIdWidth = 4,
parameter bit SwapEndianess = 0, // swap endianess in l15 adapter
parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig
) (
input logic clk_i,
@ -570,7 +568,6 @@ module ariane #(
`ifdef WT_DCACHE
// this is a cache subsystem that is compatible with OpenPiton
wt_cache_subsystem #(
.AxiIdWidth ( AxiIdWidth ),
.ArianeCfg ( ArianeCfg )
) i_cache_subsystem (
// to D$

15
src/cache_subsystem/wt_axi_adapter.sv
View file

@ -18,8 +18,7 @@ import wt_cache_pkg::*;
module wt_axi_adapter #(
parameter int unsigned ReqFifoDepth = 2,
parameter int unsigned MetaFifoDepth = wt_cache_pkg::DCACHE_MAX_TX,
parameter int unsigned AxiIdWidth = 4
parameter int unsigned MetaFifoDepth = wt_cache_pkg::DCACHE_MAX_TX
) (
input logic clk_i,
input logic rst_ni,
@ -69,7 +68,7 @@ module wt_axi_adapter #(
logic [63:0] axi_rd_addr, axi_wr_addr;
logic [$clog2(AxiNumWords)-1:0] axi_rd_blen, axi_wr_blen;
logic [1:0] axi_rd_size, axi_wr_size;
logic [AxiIdWidth-1:0] axi_rd_id_in, axi_wr_id_in, axi_rd_id_out, axi_wr_id_out, wr_id_out;
logic [$size(axi_resp_i.r.id)-1:0] axi_rd_id_in, axi_wr_id_in, axi_rd_id_out, axi_wr_id_out, wr_id_out;
logic [AxiNumWords-1:0][63:0] axi_wr_data;
logic [63:0] axi_rd_data;
logic [AxiNumWords-1:0][7:0] axi_wr_be;
@ -334,9 +333,9 @@ module wt_axi_adapter #(
assign b_push = axi_wr_valid & axi_wr_rdy;
fifo_v3 #(
.DATA_WIDTH ( AxiIdWidth + 1 ),
.DEPTH ( MetaFifoDepth ),
.FALL_THROUGH ( 1'b1 )
.DATA_WIDTH ( $size(axi_resp_i.r.id) + 1 ),
.DEPTH ( MetaFifoDepth ),
.FALL_THROUGH ( 1'b1 )
) i_b_fifo (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
@ -538,8 +537,8 @@ module wt_axi_adapter #(
///////////////////////////////////////////////////////
axi_shim #(
.AxiNumWords ( AxiNumWords ),
.AxiIdWidth ( AxiIdWidth )
.AxiNumWords ( AxiNumWords ),
.AxiIdWidth ( $size(axi_resp_i.r.id) )
) i_axi_shim (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),

5
src/cache_subsystem/wt_cache_subsystem.sv
View file

@ -22,7 +22,6 @@ import ariane_pkg::*;
import wt_cache_pkg::*;
module wt_cache_subsystem #(
parameter int unsigned AxiIdWidth = 10,
parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig // contains cacheable regions
) (
input logic clk_i,
@ -148,9 +147,7 @@ module wt_cache_subsystem #(
.l15_rtrn_i ( l15_rtrn_i )
);
`else
wt_axi_adapter #(
.AxiIdWidth ( AxiIdWidth )
) i_adapter (
wt_axi_adapter i_adapter (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.icache_data_req_i ( icache_adapter_data_req ),

1
tb/ariane_testharness.sv
View file

@ -659,7 +659,6 @@ module ariane_testharness #(
ariane_axi::resp_t axi_ariane_resp;
ariane #(
.AxiIdWidth ( ariane_soc::IdWidth ),
.ArianeCfg ( ariane_soc::ArianeSocCfg )
) i_ariane (
.clk_i ( clk_i ),