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Generate illegal exception when accessing CSR Trigger CSRs (#1577)
CSR_TSELECT, CSR_TDATA1, CSR_TDATA2, CSR_TDATA3 are not implemented yet. Gen exception when accessing these CSRs.
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1 changed files with 8 additions and 8 deletions
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@ -229,10 +229,10 @@ module csr_regfile
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riscv::CSR_DSCRATCH0: csr_rdata = dscratch0_q;
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riscv::CSR_DSCRATCH1: csr_rdata = dscratch1_q;
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// trigger module registers
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riscv::CSR_TSELECT: ; // not implemented
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riscv::CSR_TDATA1: ; // not implemented
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riscv::CSR_TDATA2: ; // not implemented
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riscv::CSR_TDATA3: ; // not implemented
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riscv::CSR_TSELECT: read_access_exception = 1'b1; // not implemented
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riscv::CSR_TDATA1: read_access_exception = 1'b1; // not implemented
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riscv::CSR_TDATA2: read_access_exception = 1'b1; // not implemented
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riscv::CSR_TDATA3: read_access_exception = 1'b1; // not implemented
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// supervisor registers
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riscv::CSR_SSTATUS: begin
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if (CVA6Cfg.RVS)
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@ -674,10 +674,10 @@ module csr_regfile
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riscv::CSR_DSCRATCH0: dscratch0_d = csr_wdata;
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riscv::CSR_DSCRATCH1: dscratch1_d = csr_wdata;
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// trigger module CSRs
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riscv::CSR_TSELECT: ; // not implemented
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riscv::CSR_TDATA1: ; // not implemented
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riscv::CSR_TDATA2: ; // not implemented
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riscv::CSR_TDATA3: ; // not implemented
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riscv::CSR_TSELECT: update_access_exception = 1'b1 ; // not implemented
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riscv::CSR_TDATA1: update_access_exception = 1'b1; // not implemented
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riscv::CSR_TDATA2: update_access_exception = 1'b1; // not implemented
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riscv::CSR_TDATA3: update_access_exception = 1'b1; // not implemented
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// sstatus is a subset of mstatus - mask it accordingly
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riscv::CSR_SSTATUS: begin
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if (CVA6Cfg.RVS) begin
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