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Instantiated load unit
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Florian Zaruba
parent
edd4665fb5
commit
7b00a92bed
3 changed files with 112 additions and 50 deletions
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@ -275,7 +275,7 @@ module load_unit (
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)
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fifo_i (
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.full_o ( ), // we can ignore the full signal, the FIFO will never overflow
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.empty_o ( empty ), // we can ignore the empty signal, we don't care about it, we will never pop an empty FIFO
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.empty_o ( empty ),
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.single_element_o ( ), // we don't care about the single element either
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.data_i ( in_data ),
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154
src/lsu.sv
154
src/lsu.sv
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@ -100,18 +100,39 @@ module lsu #(
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logic [7:0] be_i;
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assign vaddr_i = $signed(imm_i) + $signed(operand_a_i);
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logic st_valid_i;
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logic st_ready_o;
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logic ld_valid_i;
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logic ld_ready_o;
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logic ld_translation_req;
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logic st_translation_req;
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logic [63:0] ld_vaddr;
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logic [63:0] st_vaddr;
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logic translation_req;
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logic [63:0] mmu_vaddr;
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logic ld_valid;
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logic [TRANS_ID_BITS-1:0] ld_trans_id;
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logic [63:0] ld_result;
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logic st_valid;
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logic [TRANS_ID_BITS-1:0] st_trans_id;
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logic [63:0] st_result;
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logic [11:0] page_offset;
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logic page_offset_matches;
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// ---------------
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// Memory Arbiter
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// ---------------
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logic [2:0][63:0] address_i;
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logic [2:0][63:0] data_wdata_i;
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logic [2:0] data_req_i;
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logic [2:0] data_we_i;
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logic [2:0][7:0] data_be_i;
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logic [2:0][1:0] data_tag_status_i;
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logic [2:0] data_gnt_o;
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logic [2:0] data_rvalid_o;
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logic [2:0][63:0] data_rdata_o;
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logic [2:0][63:0] address_i;
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logic [2:0][63:0] data_wdata_i;
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logic [2:0] data_req_i;
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logic [2:0] data_we_i;
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logic [2:0][7:0] data_be_i;
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logic [2:0][1:0] data_tag_status_i;
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logic [2:0] data_gnt_o;
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logic [2:0] data_rvalid_o;
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logic [2:0][63:0] data_rdata_o;
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// Port 0: PTW
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// Port 1: Load Unit
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@ -149,7 +170,7 @@ module lsu #(
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.ASID_WIDTH ( ASID_WIDTH )
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) mmu_i (
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.lsu_req_i ( translation_req ),
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.lsu_vaddr_i ( ),
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.lsu_vaddr_i ( mmu_vaddr ),
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.lsu_valid_o ( translation_valid ),
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.lsu_paddr_o ( paddr ),
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// connecting PTW to D$ IF (aka mem arbiter
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@ -164,16 +185,6 @@ module lsu #(
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.data_if_data_rdata_i ( data_rdata_o [0] ),
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.*
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);
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logic st_valid_i;
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logic st_ready_o;
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logic ld_valid;
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logic [TRANS_ID_BITS-1:0] ld_trans_id;
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logic [63:0] ld_result;
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logic st_valid;
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logic [TRANS_ID_BITS-1:0] st_trans_id;
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logic [63:0] st_result;
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// ------------------
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// Store Unit
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// ------------------
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@ -189,13 +200,13 @@ module lsu #(
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.trans_id_o ( st_trans_id ),
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.result_o ( st_result ),
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// MMU port
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.translation_req_o ( ),
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.vaddr_o ( ),
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.paddr_i ( ),
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.translation_valid_i ( ),
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.translation_req_o ( st_translation_req ),
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.vaddr_o ( st_vaddr ),
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.paddr_i ( paddr ),
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.translation_valid_i ( translation_valid ),
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// Load Unit
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.page_offset_i ( ),
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.page_offset_matches_o ( ),
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.page_offset_i ( page_offset ),
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.page_offset_matches_o ( page_offset_matches ),
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// Mem Arbiter
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.address_o ( address_i [2] ),
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.data_wdata_o ( data_wdata_i [2] ),
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@ -212,43 +223,94 @@ module lsu #(
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// Load Unit
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// ------------------
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logic vaddr_o;
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logic [63:0] paddr_i;
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logic translation_valid_i;
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load_unit load_unit_i (
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.operator_i ( operator ),
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.trans_id_i ( trans_id ),
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.valid_i ( ld_valid_i ),
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.vaddr_i ( vaddr ),
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.be_i ( be ),
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.valid_o ( ld_valid ),
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.ready_o ( ld_ready_o ),
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.trans_id_o ( ld_trans_id ),
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.result_o ( ld_result ),
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.translation_req_o ( ld_translation_req ),
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.vaddr_o ( ld_vaddr ),
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.paddr_i ( paddr ),
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.translation_valid_i ( translation_valid ),
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.page_offset_o ( page_offset ),
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.page_offset_matches_i ( page_offset_matches ),
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.address_o ( address_i [1] ),
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.data_wdata_o ( data_wdata_i [1] ),
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.data_req_o ( data_req_i [1] ),
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.data_we_o ( data_we_i [1] ),
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.data_be_o ( data_be_i [1] ),
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.data_tag_status_o ( data_tag_status_i[1] ),
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.data_gnt_i ( data_gnt_o [1] ),
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.data_rvalid_i ( data_rvalid_o [1] ),
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.data_rdata_i ( data_rdata_o [1] ),
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.*
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);
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// ---------------------
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// Result Sequentialize
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// ---------------------
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lsu_arbiter lsu_arbiter_i (
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.flush_i ( flush_i ),
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.ld_valid_i ( ld_valid ),
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.ld_trans_id_i ( ld_trans_id ),
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.ld_result_i ( ld_result ),
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.st_valid_i ( st_valid ),
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.st_trans_id_i ( st_trans_id ),
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.st_result_i ( st_result ),
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.valid_o ( lsu_valid_o ),
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.trans_id_o ( lsu_trans_id_o ),
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.result_o ( lsu_result_o )
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.flush_i ( flush_i ),
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.ld_valid_i ( ld_valid ),
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.ld_trans_id_i ( ld_trans_id ),
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.ld_result_i ( ld_result ),
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.st_valid_i ( st_valid ),
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.st_trans_id_i ( st_trans_id ),
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.st_result_i ( st_result ),
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.valid_o ( lsu_valid_o ),
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.trans_id_o ( lsu_trans_id_o ),
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.result_o ( lsu_result_o )
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);
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// ------------------
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// LSU Control
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// ------------------
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// is the operation a load or store or nothing of relevance for the LSU
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enum logic [1:0] { NONE, LD_OP, ST_OP } op;
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always_comb begin : lsu_control
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// the LSU is ready if both, stores and loads are ready because we do not know
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// which of the two we are getting
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lsu_ready_o = ld_ready_o && st_ready_o;
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// "arbitrate" MMU access, there is only one request possible
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translation_req = 1'b0;
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mmu_vaddr = 64'b0;
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if (st_translation_req) begin
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mmu_vaddr = st_vaddr;
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end else if (ld_translation_req) begin
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mmu_vaddr = ld_vaddr;
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end
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end
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enum logic {LD_OP, ST_OP} op;
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// determine whether this is a load or store
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always_comb begin : which_op
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unique case (operator_i)
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ld_valid_i = 1'b0;
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st_valid_i = 1'b0;
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unique case (operator)
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// all loads go here
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LD, LW, LWU, LH, LHU, LB, LBU: op = LD_OP;
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LD, LW, LWU, LH, LHU, LB, LBU: begin
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ld_valid_i = 1'b1;
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op = LD_OP;
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end
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// all stores go here
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SD, SW, SH, SB: op = ST_OP;
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SD, SW, SH, SB: begin
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st_valid_i = 1'b1;
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op = ST_OP;
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end
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// not relevant for the lsu
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default: op = NONE;
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default: ;
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endcase
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end
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@ -97,10 +97,10 @@ module store_queue (
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// we can issue this instruction
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// we can issue it as soon as the commit_i goes high or any number of cycles later
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// by looking at the is_speculative flag
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if (commit_queue_q.valid & (~commit_queue_q.is_speculative | commit_i)) begin
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if (commit_queue_q.valid && (~commit_queue_q.is_speculative || commit_i)) begin
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data_req_o = 1'b1;
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if (data_gnt_i) begin// advance to the next state if we received the grant
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// NS = WAIT_RVALID;
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// advance to the next state if we received the grant
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if (data_gnt_i) begin
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// we can evict it from the commit buffer
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commit_queue_n.valid = 1'b0;
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end
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