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https://github.com/openhwgroup/cva6.git
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Connect flush signal when setting Debug PC
This commit is contained in:
Florian Zaruba
parent
52794c87be
commit
81780e003d
3 changed files with 63 additions and 61 deletions
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@ -241,7 +241,7 @@ module ariane
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// Debug <-> *
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// --------------
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logic [63:0] pc_debug_pcgen;
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logic set_pc_debug_pcgen;
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logic set_pc_debug;
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logic gpr_req_debug_issue;
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logic [4:0] gpr_addr_debug_issue;
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@ -275,7 +275,7 @@ module ariane
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.trap_vector_base_i ( trap_vector_base_commit_pcgen ),
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.ex_valid_i ( ex_commit.valid ),
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.debug_pc_i ( pc_debug_pcgen ),
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.debug_set_pc_i ( set_pc_debug_pcgen ),
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.debug_set_pc_i ( set_pc_debug ),
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.*
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);
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// ---------
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@ -331,58 +331,62 @@ module ariane
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// ---------
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// Issue
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// ---------
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issue_stage
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#(
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issue_stage #(
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.NR_ENTRIES ( NR_SB_ENTRIES ),
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.NR_WB_PORTS ( NR_WB_PORTS )
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)
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issue_stage_i (
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.flush_unissued_instr_i ( flush_unissued_instr_ctrl_id ),
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.flush_i ( flush_ctrl_id ),
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) issue_stage_i (
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.flush_unissued_instr_i ( flush_unissued_instr_ctrl_id ),
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.flush_i ( flush_ctrl_id ),
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// Debug
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.debug_gpr_req_i ( gpr_req_debug_issue ),
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.debug_gpr_addr_i ( gpr_addr_debug_issue ),
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.debug_gpr_we_i ( gpr_we_debug_issue ),
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.debug_gpr_wdata_i ( gpr_wdata_debug_issue ),
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.debug_gpr_rdata_o ( gpr_rdata_debug_issue ),
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.decoded_instr_i ( issue_entry_id_issue ),
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.decoded_instr_valid_i ( issue_entry_valid_id_issue ),
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.is_ctrl_flow_i ( is_ctrl_fow_id_issue ),
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.decoded_instr_ack_o ( issue_instr_issue_id ),
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.decoded_instr_i ( issue_entry_id_issue ),
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.decoded_instr_valid_i ( issue_entry_valid_id_issue ),
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.is_ctrl_flow_i ( is_ctrl_fow_id_issue ),
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.decoded_instr_ack_o ( issue_instr_issue_id ),
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// Functional Units
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.fu_o ( fu_id_ex ),
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.operator_o ( operator_id_ex ),
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.operand_a_o ( operand_a_id_ex ),
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.operand_b_o ( operand_b_id_ex ),
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.imm_o ( imm_id_ex ),
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.trans_id_o ( trans_id_id_ex ),
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.pc_o ( pc_id_ex ),
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.is_compressed_instr_o ( is_compressed_instr_id_ex ),
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.fu_o ( fu_id_ex ),
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.operator_o ( operator_id_ex ),
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.operand_a_o ( operand_a_id_ex ),
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.operand_b_o ( operand_b_id_ex ),
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.imm_o ( imm_id_ex ),
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.trans_id_o ( trans_id_id_ex ),
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.pc_o ( pc_id_ex ),
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.is_compressed_instr_o ( is_compressed_instr_id_ex ),
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// ALU
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.alu_ready_i ( alu_ready_ex_id ),
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.alu_valid_o ( alu_valid_id_ex ),
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.alu_ready_i ( alu_ready_ex_id ),
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.alu_valid_o ( alu_valid_id_ex ),
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// Branches and Jumps
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.branch_ready_i ( branch_ready_ex_id ),
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.branch_valid_o ( branch_valid_id_ex ), // branch is valid
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.branch_predict_o ( branch_predict_id_ex ), // branch predict to ex
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.resolve_branch_i ( resolve_branch_ex_id ), // in order to resolve the branch
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.branch_ready_i ( branch_ready_ex_id ),
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.branch_valid_o ( branch_valid_id_ex ), // branch is valid
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.branch_predict_o ( branch_predict_id_ex ), // branch predict to ex
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.resolve_branch_i ( resolve_branch_ex_id ), // in order to resolve the branch
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// LSU
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.lsu_ready_i ( lsu_ready_ex_id ),
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.lsu_valid_o ( lsu_valid_id_ex ),
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.lsu_ready_i ( lsu_ready_ex_id ),
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.lsu_valid_o ( lsu_valid_id_ex ),
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// Multiplier
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.mult_ready_i ( mult_ready_ex_id ),
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.mult_valid_o ( mult_valid_id_ex ),
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.mult_ready_i ( mult_ready_ex_id ),
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.mult_valid_o ( mult_valid_id_ex ),
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// CSR
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.csr_ready_i ( csr_ready_ex_id ),
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.csr_valid_o ( csr_valid_id_ex ),
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.csr_ready_i ( csr_ready_ex_id ),
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.csr_valid_o ( csr_valid_id_ex ),
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.trans_id_i ( {alu_trans_id_ex_id, lsu_trans_id_ex_id, branch_trans_id_ex_id, csr_trans_id_ex_id }),
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.wdata_i ( {alu_result_ex_id, lsu_result_ex_id, branch_result_ex_id, csr_result_ex_id }),
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.ex_ex_i ( {{$bits(exception){1'b0}}, lsu_exception_ex_id, branch_exception_ex_id, {$bits(exception){1'b0}} }),
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.wb_valid_i ( {alu_valid_ex_id, lsu_valid_ex_id, branch_valid_ex_id, csr_valid_ex_id }),
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.waddr_a_i ( waddr_a_commit_id ),
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.wdata_a_i ( wdata_a_commit_id ),
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.we_a_i ( we_a_commit_id ),
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.waddr_a_i ( waddr_a_commit_id ),
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.wdata_a_i ( wdata_a_commit_id ),
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.we_a_i ( we_a_commit_id ),
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.commit_instr_o ( commit_instr_id_commit ),
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.commit_ack_i ( commit_ack ),
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.commit_instr_o ( commit_instr_id_commit ),
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.commit_ack_i ( commit_ack ),
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.*
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);
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@ -529,6 +533,7 @@ module ariane
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.halt_csr_i ( halt_csr_ctrl ),
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.halt_debug_i ( halt_debug_ctrl ),
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.debug_set_pc_i ( set_pc_debug ),
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.halt_o ( halt_ctrl_commit ),
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// control ports
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.eret_i ( eret ),
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@ -540,6 +545,7 @@ module ariane
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.*
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);
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// ------------
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// Debug
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// ------------
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@ -550,7 +556,7 @@ module ariane
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.halt_o ( halt_debug_ctrl ),
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.debug_pc_o ( pc_debug_pcgen ),
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.debug_set_pc_o ( debug_set_pc_o ),
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.debug_set_pc_o ( set_pc_debug ),
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.debug_gpr_req_o ( gpr_req_debug_issue ),
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.debug_gpr_addr_o ( gpr_addr_debug_issue ),
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@ -31,6 +31,7 @@ module controller (
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input logic halt_csr_i, // Halt request from CSR (WFI instruction)
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input logic halt_debug_i, // Halt request from debug
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input logic debug_set_pc_i, // Debug wants to set the PC
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output logic halt_o, // Halt signal to commit stage
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input logic eret_i, // Return from exception
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input logic ex_valid_i, // We got an exception, flush the pipeline
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@ -64,13 +65,13 @@ module controller (
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flush_if_o = 1'b1;
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end
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// ----------------------
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// ---------------------------------
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// FENCE
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// ----------------------
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// ---------------------------------
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// ----------------------
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// ---------------------------------
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// FENCE.I
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// ----------------------
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// ---------------------------------
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if (fence_i_i) begin
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flush_pcgen_o = 1'b1;
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flush_if_o = 1'b1;
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@ -79,9 +80,9 @@ module controller (
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flush_ex_o = 1'b1;
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flush_icache_o = 1'b1;
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end
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// ----------------------
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// ---------------------------------
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// SFENCE.VMA
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// ----------------------
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// ---------------------------------
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if (sfence_vma_i) begin
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flush_pcgen_o = 1'b1;
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flush_if_o = 1'b1;
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@ -102,10 +103,12 @@ module controller (
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flush_ex_o = 1'b1;
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end
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// ------------
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// Exception
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// ------------
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if (ex_valid_i) begin
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// ---------------------------------
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// 1. Exception
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// 2. Return from exception
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// 3. Debug
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// ---------------------------------
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if (ex_valid_i || eret_i || debug_set_pc_i) begin
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// don't flush pcgen as we want to take the exception, flush pcgen is not a flush signal
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// for the PC GEN stage but instead tells it to take the PC we gave it
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flush_pcgen_o = 1'b0;
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@ -114,19 +117,6 @@ module controller (
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flush_id_o = 1'b1;
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flush_ex_o = 1'b1;
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end
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// ----------------------
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// Return from exception
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// ----------------------
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if (eret_i) begin
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// don't flush pcgen as we want to take the exception
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flush_pcgen_o = 1'b0;
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flush_if_o = 1'b1;
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flush_unissued_instr_o = 1'b1;
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flush_id_o = 1'b1;
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flush_ex_o = 1'b1;
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end
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end
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// ----------------------
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@ -31,6 +31,12 @@ module issue_stage #(
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input logic flush_unissued_instr_i,
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input logic flush_i,
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// from Debug
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input logic debug_gpr_req_i,
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input logic [4:0] debug_gpr_addr_i,
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input logic debug_gpr_we_i,
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input logic [63:0] debug_gpr_wdata_i,
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output logic [63:0] debug_gpr_rdata_o,
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// from ISSUE
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input scoreboard_entry decoded_instr_i,
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input logic decoded_instr_valid_i,
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