mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-19 11:54:46 -04:00
Add Exclusive Adapter (#187)
* Add atomic adapter as submodule * Change UART frequency * Add atomic memory adapter * Bump AXI exclusive submodule version * Re-name ariane_next to ariane-dev * Switch to official `atop` branch on `axi_node`
This commit is contained in:
Florian Zaruba
parent
b1bdc0c02c
commit
843300302f
11 changed files with 104 additions and 191 deletions
3
.gitmodules
vendored
3
.gitmodules
vendored
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@ -40,3 +40,6 @@
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[submodule "fpga/src/ariane-ethernet"]
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path = fpga/src/ariane-ethernet
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url = https://github.com/lowRISC/ariane-ethernet.git
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[submodule "src/axi_riscv_atomics"]
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path = src/axi_riscv_atomics
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url = https://github.com/pulp-platform/axi_riscv_atomics.git
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@ -41,7 +41,7 @@ env:
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branches:
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only:
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- master
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- ariane_next
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- ariane-dev
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before_install:
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- export CXX=g++-7 CC=gcc-7
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@ -72,7 +72,7 @@ jobs:
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name: build gcc
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script:
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- ci/build-riscv-gcc.sh 1
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- rm -rf $RISCV/riscv-gnu-toolchain
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- rm -rf $RISCV/riscv-gnu-toolchain
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- stage: compile2
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name: build tools
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script:
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1
Makefile
1
Makefile
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@ -90,6 +90,7 @@ src := $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) \
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$(wildcard fpga/src/axi_slice/src/*.sv) \
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$(wildcard src/plic/*.sv) \
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$(wildcard src/axi_node/src/*.sv) \
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$(wildcard src/axi_riscv_atomics/src/*.sv) \
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$(wildcard src/axi_mem_if/src/*.sv) \
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$(filter-out src/debug/dm_pkg.sv, $(wildcard src/debug/*.sv)) \
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$(wildcard src/debug/debug_rom/*.sv) \
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@ -209,7 +209,8 @@ axi_node_wrap_with_slices #(
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ariane_soc::EthernetBase + ariane_soc::EthernetLength -1,
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ariane_soc::GPIOBase + ariane_soc::GPIOLength - 1,
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ariane_soc::DRAMBase + ariane_soc::DRAMLength - 1
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})
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}),
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.valid_rule_i ('1)
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);
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// ---------------
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@ -446,51 +447,72 @@ logic s_axi_rlast;
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logic s_axi_rvalid;
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logic s_axi_rready;
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assign master[ariane_soc::DRAM].r_user = '0;
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assign master[ariane_soc::DRAM].b_user = '0;
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AXI_BUS #(
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.AXI_ADDR_WIDTH ( AxiAddrWidth ),
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.AXI_DATA_WIDTH ( AxiDataWidth ),
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.AXI_ID_WIDTH ( AxiIdWidthSlaves ),
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.AXI_USER_WIDTH ( AxiUserWidth )
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) dram();
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axi_riscv_atomics #(
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.AXI_ADDR_WIDTH ( AxiAddrWidth ),
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.AXI_DATA_WIDTH ( AxiDataWidth ),
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.AXI_ID_WIDTH ( AxiIdWidthSlaves ),
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.AXI_USER_WIDTH ( AxiUserWidth ),
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.AXI_MAX_WRITE_TXNS ( 1 ),
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.RISCV_WORD_WIDTH ( 64 )
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) i_axi_riscv_atomics (
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.clk_i ( clk ),
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.rst_ni ( ndmreset_n ),
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.slv ( master[ariane_soc::DRAM] ),
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.mst ( dram )
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);
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assign dram.r_user = '0;
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assign dram.b_user = '0;
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xlnx_axi_clock_converter i_xlnx_axi_clock_converter_ddr (
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.s_axi_aclk ( clk ),
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.s_axi_aresetn ( ndmreset_n ),
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.s_axi_awid ( master[ariane_soc::DRAM].aw_id ),
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.s_axi_awaddr ( master[ariane_soc::DRAM].aw_addr ),
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.s_axi_awlen ( master[ariane_soc::DRAM].aw_len ),
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.s_axi_awsize ( master[ariane_soc::DRAM].aw_size ),
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.s_axi_awburst ( master[ariane_soc::DRAM].aw_burst ),
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.s_axi_awlock ( master[ariane_soc::DRAM].aw_lock ),
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.s_axi_awcache ( master[ariane_soc::DRAM].aw_cache ),
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.s_axi_awprot ( master[ariane_soc::DRAM].aw_prot ),
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.s_axi_awregion ( master[ariane_soc::DRAM].aw_region ),
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.s_axi_awqos ( master[ariane_soc::DRAM].aw_qos ),
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.s_axi_awvalid ( master[ariane_soc::DRAM].aw_valid ),
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.s_axi_awready ( master[ariane_soc::DRAM].aw_ready ),
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.s_axi_wdata ( master[ariane_soc::DRAM].w_data ),
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.s_axi_wstrb ( master[ariane_soc::DRAM].w_strb ),
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.s_axi_wlast ( master[ariane_soc::DRAM].w_last ),
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.s_axi_wvalid ( master[ariane_soc::DRAM].w_valid ),
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.s_axi_wready ( master[ariane_soc::DRAM].w_ready ),
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.s_axi_bid ( master[ariane_soc::DRAM].b_id ),
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.s_axi_bresp ( master[ariane_soc::DRAM].b_resp ),
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.s_axi_bvalid ( master[ariane_soc::DRAM].b_valid ),
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.s_axi_bready ( master[ariane_soc::DRAM].b_ready ),
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.s_axi_arid ( master[ariane_soc::DRAM].ar_id ),
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.s_axi_araddr ( master[ariane_soc::DRAM].ar_addr ),
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.s_axi_arlen ( master[ariane_soc::DRAM].ar_len ),
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.s_axi_arsize ( master[ariane_soc::DRAM].ar_size ),
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.s_axi_arburst ( master[ariane_soc::DRAM].ar_burst ),
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.s_axi_arlock ( master[ariane_soc::DRAM].ar_lock ),
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.s_axi_arcache ( master[ariane_soc::DRAM].ar_cache ),
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.s_axi_arprot ( master[ariane_soc::DRAM].ar_prot ),
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.s_axi_arregion ( master[ariane_soc::DRAM].ar_region ),
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.s_axi_arqos ( master[ariane_soc::DRAM].ar_qos ),
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.s_axi_arvalid ( master[ariane_soc::DRAM].ar_valid ),
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.s_axi_arready ( master[ariane_soc::DRAM].ar_ready ),
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.s_axi_rid ( master[ariane_soc::DRAM].r_id ),
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.s_axi_rdata ( master[ariane_soc::DRAM].r_data ),
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.s_axi_rresp ( master[ariane_soc::DRAM].r_resp ),
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.s_axi_rlast ( master[ariane_soc::DRAM].r_last ),
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.s_axi_rvalid ( master[ariane_soc::DRAM].r_valid ),
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.s_axi_rready ( master[ariane_soc::DRAM].r_ready ),
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.s_axi_aclk ( clk ),
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.s_axi_aresetn ( ndmreset_n ),
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.s_axi_awid ( dram.aw_id ),
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.s_axi_awaddr ( dram.aw_addr ),
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.s_axi_awlen ( dram.aw_len ),
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.s_axi_awsize ( dram.aw_size ),
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.s_axi_awburst ( dram.aw_burst ),
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.s_axi_awlock ( dram.aw_lock ),
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.s_axi_awcache ( dram.aw_cache ),
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.s_axi_awprot ( dram.aw_prot ),
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.s_axi_awregion ( dram.aw_region ),
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.s_axi_awqos ( dram.aw_qos ),
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.s_axi_awvalid ( dram.aw_valid ),
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.s_axi_awready ( dram.aw_ready ),
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.s_axi_wdata ( dram.w_data ),
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.s_axi_wstrb ( dram.w_strb ),
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.s_axi_wlast ( dram.w_last ),
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.s_axi_wvalid ( dram.w_valid ),
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.s_axi_wready ( dram.w_ready ),
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.s_axi_bid ( dram.b_id ),
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.s_axi_bresp ( dram.b_resp ),
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.s_axi_bvalid ( dram.b_valid ),
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.s_axi_bready ( dram.b_ready ),
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.s_axi_arid ( dram.ar_id ),
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.s_axi_araddr ( dram.ar_addr ),
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.s_axi_arlen ( dram.ar_len ),
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.s_axi_arsize ( dram.ar_size ),
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.s_axi_arburst ( dram.ar_burst ),
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.s_axi_arlock ( dram.ar_lock ),
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.s_axi_arcache ( dram.ar_cache ),
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.s_axi_arprot ( dram.ar_prot ),
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.s_axi_arregion ( dram.ar_region ),
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.s_axi_arqos ( dram.ar_qos ),
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.s_axi_arvalid ( dram.ar_valid ),
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.s_axi_arready ( dram.ar_ready ),
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.s_axi_rid ( dram.r_id ),
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.s_axi_rdata ( dram.r_data ),
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.s_axi_rresp ( dram.r_resp ),
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.s_axi_rlast ( dram.r_last ),
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.s_axi_rvalid ( dram.r_valid ),
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.s_axi_rready ( dram.r_ready ),
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// to size converter
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.m_axi_aclk ( ddr_clock_out ),
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.m_axi_aresetn ( ndmreset_n ),
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@ -548,7 +570,7 @@ xlnx_clk_gen i_xlnx_clk_gen (
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fan_ctrl i_fan_ctrl (
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.clk_i ( clk ),
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.rst_ni ( ndmreset_n ),
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.pwm_setting_i ( sw[3:0] ),
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.pwm_setting_i ( '1 ),
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.fan_pwm_o ( fan_pwm )
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);
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@ -31,6 +31,7 @@ interface AXI_BUS #(
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typedef logic [AXI_DATA_WIDTH-1:0] data_t;
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typedef logic [AXI_STRB_WIDTH-1:0] strb_t;
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typedef logic [AXI_USER_WIDTH-1:0] user_t;
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typedef logic [5:0] atop_t;
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id_t aw_id;
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addr_t aw_addr;
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@ -41,6 +42,7 @@ interface AXI_BUS #(
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cache_t aw_cache;
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prot_t aw_prot;
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qos_t aw_qos;
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atop_t aw_atop;
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region_t aw_region;
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user_t aw_user;
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logic aw_valid;
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@ -82,7 +84,7 @@ interface AXI_BUS #(
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logic r_ready;
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modport Master (
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output aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_user, aw_valid, input aw_ready,
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output aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_atop, aw_region, aw_user, aw_valid, input aw_ready,
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output w_data, w_strb, w_last, w_user, w_valid, input w_ready,
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input b_id, b_resp, b_user, b_valid, output b_ready,
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output ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_valid, input ar_ready,
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@ -90,7 +92,7 @@ interface AXI_BUS #(
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);
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modport Slave (
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input aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_user, aw_valid, output aw_ready,
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input aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_atop, aw_region, aw_user, aw_valid, output aw_ready,
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input w_data, w_strb, w_last, w_user, w_valid, output w_ready,
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output b_id, b_resp, b_user, b_valid, input b_ready,
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input ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_valid, output ar_ready,
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@ -99,7 +101,7 @@ interface AXI_BUS #(
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/// The interface as an output (issuing requests, initiator, master).
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modport out (
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output aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_user, aw_valid, input aw_ready,
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output aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_atop, aw_region, aw_user, aw_valid, input aw_ready,
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output w_data, w_strb, w_last, w_user, w_valid, input w_ready,
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input b_id, b_resp, b_user, b_valid, output b_ready,
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output ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_valid, input ar_ready,
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@ -108,7 +110,7 @@ interface AXI_BUS #(
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/// The interface as an input (accepting requests, target, slave).
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modport in (
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input aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_user, aw_valid, output aw_ready,
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input aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_atop, aw_region, aw_user, aw_valid, output aw_ready,
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input w_data, w_strb, w_last, w_user, w_valid, output w_ready,
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output b_id, b_resp, b_user, b_valid, input b_ready,
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input ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_valid, output ar_ready,
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@ -140,6 +142,7 @@ interface AXI_BUS_ASYNC
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logic [3:0] aw_cache;
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logic [2:0] aw_prot;
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logic [3:0] aw_qos;
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logic [5:0] aw_atop;
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logic [3:0] aw_region;
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logic [AXI_USER_WIDTH-1:0] aw_user;
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logic [BUFFER_WIDTH-1:0] aw_writetoken;
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@ -181,7 +184,7 @@ interface AXI_BUS_ASYNC
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logic [BUFFER_WIDTH-1:0] r_readpointer;
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modport Master (
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output aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_user, aw_writetoken, input aw_readpointer,
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output aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_atop, aw_region, aw_user, aw_writetoken, input aw_readpointer,
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output w_data, w_strb, w_last, w_user, w_writetoken, input w_readpointer,
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input b_id, b_resp, b_user, b_writetoken, output b_readpointer,
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output ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_writetoken, input ar_readpointer,
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@ -189,7 +192,7 @@ interface AXI_BUS_ASYNC
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);
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modport Slave (
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input aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_user, aw_writetoken, output aw_readpointer,
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input aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_atop, aw_region, aw_user, aw_writetoken, output aw_readpointer,
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input w_data, w_strb, w_last, w_user, w_writetoken, output w_readpointer,
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output b_id, b_resp, b_user, b_writetoken, input b_readpointer,
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input ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_writetoken, output ar_readpointer,
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2
src/axi
2
src/axi
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@ -1 +1 @@
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Subproject commit d94d601e55213d770beceebfab7786adf7baf8ce
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Subproject commit 8140a2aa21e991271741b9865f0b0beea4a73999
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@ -1 +1 @@
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Subproject commit 6338af6ee3065c4de22b555a67f64755745b7129
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Subproject commit a29a69a543e96d0c9f79ea9c7df20580b3da5002
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1
src/axi_riscv_atomics
Submodule
1
src/axi_riscv_atomics
Submodule
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@ -0,0 +1 @@
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Subproject commit 90729df26593ee7b6eb4f55eb2ad665b0f8d1356
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@ -26,6 +26,7 @@ module axi_master_connect (
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assign master.aw_cache = axi_req_i.aw.cache;
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assign master.aw_prot = axi_req_i.aw.prot;
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assign master.aw_qos = axi_req_i.aw.qos;
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assign master.aw_atop = axi_req_i.aw.atop;
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assign master.aw_region = axi_req_i.aw.region;
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assign master.aw_user = '0;
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assign master.aw_valid = axi_req_i.aw_valid;
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@ -17,7 +17,6 @@ module axi_slave_connect (
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AXI_BUS.in slave
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);
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assign axi_req_o.aw.atop = '0; // not supported at the moment
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assign axi_req_o.aw.id = slave.aw_id;
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assign axi_req_o.aw.addr = slave.aw_addr;
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assign axi_req_o.aw.len = slave.aw_len;
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@ -27,6 +26,7 @@ module axi_slave_connect (
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assign axi_req_o.aw.cache = slave.aw_cache;
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assign axi_req_o.aw.prot = slave.aw_prot;
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assign axi_req_o.aw.qos = slave.aw_qos;
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assign axi_req_o.aw.atop = slave.aw_atop;
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assign axi_req_o.aw.region = slave.aw_region;
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// assign = slave.aw_user;
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assign axi_req_o.aw_valid = slave.aw_valid;
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@ -242,10 +242,9 @@ module ariane_testharness #(
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.rdata_o ( rom_rdata )
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);
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// ---------------
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// Memory
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// ---------------
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// ------------------------------
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// Memory + Exclusive Access
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// ------------------------------
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AXI_BUS #(
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.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
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.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
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@ -260,138 +259,20 @@ module ariane_testharness #(
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logic [AXI_DATA_WIDTH-1:0] wdata;
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logic [AXI_DATA_WIDTH-1:0] rdata;
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axi_pkg::aw_chan_t aw_chan_i;
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axi_pkg::w_chan_t w_chan_i;
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axi_pkg::b_chan_t b_chan_o;
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axi_pkg::ar_chan_t ar_chan_i;
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axi_pkg::r_chan_t r_chan_o;
|
||||
axi_pkg::aw_chan_t aw_chan_o;
|
||||
axi_pkg::w_chan_t w_chan_o;
|
||||
axi_pkg::b_chan_t b_chan_i;
|
||||
axi_pkg::ar_chan_t ar_chan_o;
|
||||
axi_pkg::r_chan_t r_chan_i;
|
||||
|
||||
axi_delayer #(
|
||||
.aw_t ( axi_pkg::aw_chan_t ),
|
||||
.w_t ( axi_pkg::w_chan_t ),
|
||||
.b_t ( axi_pkg::b_chan_t ),
|
||||
.ar_t ( axi_pkg::ar_chan_t ),
|
||||
.r_t ( axi_pkg::r_chan_t ),
|
||||
.StallRandomOutput ( StallRandomOutput ),
|
||||
.StallRandomInput ( StallRandomInput ),
|
||||
.FixedDelayInput ( 0 ),
|
||||
.FixedDelayOutput ( 0 )
|
||||
) i_axi_delayer (
|
||||
.clk_i ( clk_i ),
|
||||
.rst_ni ( ndmreset_n ),
|
||||
.aw_valid_i ( master[ariane_soc::DRAM].aw_valid ),
|
||||
.aw_chan_i ( aw_chan_i ),
|
||||
.aw_ready_o ( master[ariane_soc::DRAM].aw_ready ),
|
||||
.w_valid_i ( master[ariane_soc::DRAM].w_valid ),
|
||||
.w_chan_i ( w_chan_i ),
|
||||
.w_ready_o ( master[ariane_soc::DRAM].w_ready ),
|
||||
.b_valid_o ( master[ariane_soc::DRAM].b_valid ),
|
||||
.b_chan_o ( b_chan_o ),
|
||||
.b_ready_i ( master[ariane_soc::DRAM].b_ready ),
|
||||
.ar_valid_i ( master[ariane_soc::DRAM].ar_valid ),
|
||||
.ar_chan_i ( ar_chan_i ),
|
||||
.ar_ready_o ( master[ariane_soc::DRAM].ar_ready ),
|
||||
.r_valid_o ( master[ariane_soc::DRAM].r_valid ),
|
||||
.r_chan_o ( r_chan_o ),
|
||||
.r_ready_i ( master[ariane_soc::DRAM].r_ready ),
|
||||
.aw_valid_o ( dram.aw_valid ),
|
||||
.aw_chan_o ( aw_chan_o ),
|
||||
.aw_ready_i ( dram.aw_ready ),
|
||||
.w_valid_o ( dram.w_valid ),
|
||||
.w_chan_o ( w_chan_o ),
|
||||
.w_ready_i ( dram.w_ready ),
|
||||
.b_valid_i ( dram.b_valid ),
|
||||
.b_chan_i ( b_chan_i ),
|
||||
.b_ready_o ( dram.b_ready ),
|
||||
.ar_valid_o ( dram.ar_valid ),
|
||||
.ar_chan_o ( ar_chan_o ),
|
||||
.ar_ready_i ( dram.ar_ready ),
|
||||
.r_valid_i ( dram.r_valid ),
|
||||
.r_chan_i ( r_chan_i ),
|
||||
.r_ready_o ( dram.r_ready )
|
||||
axi_riscv_atomics #(
|
||||
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
|
||||
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
|
||||
.AXI_ID_WIDTH ( AXI_ID_WIDTH_SLAVES ),
|
||||
.AXI_USER_WIDTH ( AXI_USER_WIDTH ),
|
||||
.AXI_MAX_WRITE_TXNS ( 1 ),
|
||||
.RISCV_WORD_WIDTH ( 64 )
|
||||
) i_axi_riscv_atomics (
|
||||
.clk_i,
|
||||
.rst_ni ( ndmreset_n ),
|
||||
.slv ( master[ariane_soc::DRAM] ),
|
||||
.mst ( dram )
|
||||
);
|
||||
|
||||
assign aw_chan_i.atop = '0;
|
||||
assign aw_chan_i.id = master[ariane_soc::DRAM].aw_id;
|
||||
assign aw_chan_i.addr = master[ariane_soc::DRAM].aw_addr;
|
||||
assign aw_chan_i.len = master[ariane_soc::DRAM].aw_len;
|
||||
assign aw_chan_i.size = master[ariane_soc::DRAM].aw_size;
|
||||
assign aw_chan_i.burst = master[ariane_soc::DRAM].aw_burst;
|
||||
assign aw_chan_i.lock = master[ariane_soc::DRAM].aw_lock;
|
||||
assign aw_chan_i.cache = master[ariane_soc::DRAM].aw_cache;
|
||||
assign aw_chan_i.prot = master[ariane_soc::DRAM].aw_prot;
|
||||
assign aw_chan_i.qos = master[ariane_soc::DRAM].aw_qos;
|
||||
assign aw_chan_i.region = master[ariane_soc::DRAM].aw_region;
|
||||
|
||||
assign ar_chan_i.id = master[ariane_soc::DRAM].ar_id;
|
||||
assign ar_chan_i.addr = master[ariane_soc::DRAM].ar_addr;
|
||||
assign ar_chan_i.len = master[ariane_soc::DRAM].ar_len;
|
||||
assign ar_chan_i.size = master[ariane_soc::DRAM].ar_size;
|
||||
assign ar_chan_i.burst = master[ariane_soc::DRAM].ar_burst;
|
||||
assign ar_chan_i.lock = master[ariane_soc::DRAM].ar_lock;
|
||||
assign ar_chan_i.cache = master[ariane_soc::DRAM].ar_cache;
|
||||
assign ar_chan_i.prot = master[ariane_soc::DRAM].ar_prot;
|
||||
assign ar_chan_i.qos = master[ariane_soc::DRAM].ar_qos;
|
||||
assign ar_chan_i.region = master[ariane_soc::DRAM].ar_region;
|
||||
|
||||
assign w_chan_i.data = master[ariane_soc::DRAM].w_data;
|
||||
assign w_chan_i.strb = master[ariane_soc::DRAM].w_strb;
|
||||
assign w_chan_i.last = master[ariane_soc::DRAM].w_last;
|
||||
|
||||
assign master[ariane_soc::DRAM].r_id = r_chan_o.id;
|
||||
assign master[ariane_soc::DRAM].r_data = r_chan_o.data;
|
||||
assign master[ariane_soc::DRAM].r_resp = r_chan_o.resp;
|
||||
assign master[ariane_soc::DRAM].r_last = r_chan_o.last;
|
||||
|
||||
assign master[ariane_soc::DRAM].b_id = b_chan_o.id;
|
||||
assign master[ariane_soc::DRAM].b_resp = b_chan_o.resp;
|
||||
|
||||
|
||||
assign dram.aw_id = aw_chan_o.id;
|
||||
assign dram.aw_addr = aw_chan_o.addr;
|
||||
assign dram.aw_len = aw_chan_o.len;
|
||||
assign dram.aw_size = aw_chan_o.size;
|
||||
assign dram.aw_burst = aw_chan_o.burst;
|
||||
assign dram.aw_lock = aw_chan_o.lock;
|
||||
assign dram.aw_cache = aw_chan_o.cache;
|
||||
assign dram.aw_prot = aw_chan_o.prot;
|
||||
assign dram.aw_qos = aw_chan_o.qos;
|
||||
assign dram.aw_region = aw_chan_o.region;
|
||||
assign dram.aw_user = master[ariane_soc::DRAM].aw_user;
|
||||
|
||||
assign dram.ar_id = ar_chan_o.id;
|
||||
assign dram.ar_addr = ar_chan_o.addr;
|
||||
assign dram.ar_len = ar_chan_o.len;
|
||||
assign dram.ar_size = ar_chan_o.size;
|
||||
assign dram.ar_burst = ar_chan_o.burst;
|
||||
assign dram.ar_lock = ar_chan_o.lock;
|
||||
assign dram.ar_cache = ar_chan_o.cache;
|
||||
assign dram.ar_prot = ar_chan_o.prot;
|
||||
assign dram.ar_qos = ar_chan_o.qos;
|
||||
assign dram.ar_region = ar_chan_o.region;
|
||||
assign dram.ar_user = master[ariane_soc::DRAM].ar_user;
|
||||
|
||||
assign dram.w_data = w_chan_o.data;
|
||||
assign dram.w_strb = w_chan_o.strb;
|
||||
assign dram.w_last = w_chan_o.last;
|
||||
assign dram.w_user = master[ariane_soc::DRAM].w_user;
|
||||
|
||||
assign r_chan_i.id = dram.r_id;
|
||||
assign r_chan_i.data = dram.r_data;
|
||||
assign r_chan_i.resp = dram.r_resp;
|
||||
assign r_chan_i.last = dram.r_last;
|
||||
assign master[ariane_soc::DRAM].r_user = dram.r_user;
|
||||
|
||||
assign b_chan_i.id = dram.b_id;
|
||||
assign b_chan_i.resp = dram.b_resp;
|
||||
assign master[ariane_soc::DRAM].b_user = dram.b_user;
|
||||
|
||||
|
||||
axi2mem #(
|
||||
.AXI_ID_WIDTH ( AXI_ID_WIDTH_SLAVES ),
|
||||
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
|
||||
|
|
@ -462,7 +343,8 @@ module ariane_testharness #(
|
|||
ariane_soc::EthernetBase + ariane_soc::EthernetLength -1,
|
||||
ariane_soc::GPIOBase + ariane_soc::GPIOLength - 1,
|
||||
ariane_soc::DRAMBase + ariane_soc::DRAMLength - 1
|
||||
})
|
||||
}),
|
||||
.valid_rule_i ('1)
|
||||
);
|
||||
|
||||
// ---------------
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue