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Fix RVFI always_ff blocks (#2053)

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MarioOpenHWGroup 2024-04-18 10:06:34 +02:00 • committed by GitHub
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commit 8a9d7a832b
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5 changed files with 79 additions and 68 deletions
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2
ci/setup.sh
View file

@ -21,7 +21,7 @@ if [ -d ${VERILATOR_BUILD_DIR} ]; then
fi
if [ -f ${SPIKE_PATH}/spike ]; then
spike_version="$(git -C ${SPIKE_SRC_DIR} log -1 --pretty=tformat:%h -- ${SPIKE_SRC_DIR}/..)"
spike_version="$(git -C ${SPIKE_SRC_DIR} log -1 --pretty=tformat:%h -- ${SPIKE_SRC_DIR}/ )"
spike_installed_version="$(${SPIKE_PATH}/spike -v |& cut -d ' ' -f 2)"
if [ "$spike_installed_version" != "$spike_version" ]; then
rm -rf ${SPIKE_INSTALL_DIR}

62
core/cva6_rvfi.sv
View file

@ -240,31 +240,32 @@ module cva6_rvfi
for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
logic exception;
exception = commit_instr_valid[i][0] && ex_commit_valid;
rvfi_instr_o[i].valid = (commit_ack[i] && !ex_commit_valid) ||
rvfi_instr_o[i].valid <= (commit_ack[i] && !ex_commit_valid) ||
(exception && (ex_commit_cause == riscv::ENV_CALL_MMODE ||
ex_commit_cause == riscv::ENV_CALL_SMODE ||
ex_commit_cause == riscv::ENV_CALL_UMODE));
rvfi_instr_o[i].insn = mem_q[commit_pointer[i]].instr;
rvfi_instr_o[i].insn <= mem_q[commit_pointer[i]].instr;
// when trap, the instruction is not executed
rvfi_instr_o[i].trap = exception;
rvfi_instr_o[i].cause = ex_commit_cause;
rvfi_instr_o[i].mode = (CVA6Cfg.DebugEn && debug_mode) ? 2'b10 : priv_lvl;
rvfi_instr_o[i].ixl = CVA6Cfg.XLEN == 64 ? 2 : 1;
rvfi_instr_o[i].rs1_addr = commit_instr_rs1[i][4:0];
rvfi_instr_o[i].rs2_addr = commit_instr_rs2[i][4:0];
rvfi_instr_o[i].rd_addr = commit_instr_rd[i][4:0];
rvfi_instr_o[i].rd_wdata = (CVA6Cfg.FpPresent && is_rd_fpr(commit_instr_op[i])) ?
commit_instr_result[i] : wdata[i];
rvfi_instr_o[i].pc_rdata = commit_instr_pc[i];
rvfi_instr_o[i].mem_addr = mem_q[commit_pointer[i]].lsu_addr;
rvfi_instr_o[i].trap <= exception;
rvfi_instr_o[i].cause <= ex_commit_cause;
rvfi_instr_o[i].mode <= (CVA6Cfg.DebugEn && debug_mode) ? 2'b10 : priv_lvl;
rvfi_instr_o[i].ixl <= CVA6Cfg.XLEN == 64 ? 2 : 1;
rvfi_instr_o[i].rs1_addr <= commit_instr_rs1[i][4:0];
rvfi_instr_o[i].rs2_addr <= commit_instr_rs2[i][4:0];
rvfi_instr_o[i].rd_addr <= commit_instr_rd[i][4:0];
rvfi_instr_o[i].rd_wdata <= (CVA6Cfg.FpPresent && is_rd_fpr(
commit_instr_op[i]
)) ? commit_instr_result[i] : wdata[i];
rvfi_instr_o[i].pc_rdata <= commit_instr_pc[i];
rvfi_instr_o[i].mem_addr <= mem_q[commit_pointer[i]].lsu_addr;
// So far, only write paddr is reported. TODO: read paddr
rvfi_instr_o[i].mem_paddr = mem_paddr;
rvfi_instr_o[i].mem_wmask = mem_q[commit_pointer[i]].lsu_wmask;
rvfi_instr_o[i].mem_wdata = mem_q[commit_pointer[i]].lsu_wdata;
rvfi_instr_o[i].mem_rmask = mem_q[commit_pointer[i]].lsu_rmask;
rvfi_instr_o[i].mem_rdata = commit_instr_result[i];
rvfi_instr_o[i].rs1_rdata = mem_q[commit_pointer[i]].rs1_rdata;
rvfi_instr_o[i].rs2_rdata = mem_q[commit_pointer[i]].rs2_rdata;
rvfi_instr_o[i].mem_paddr <= mem_paddr;
rvfi_instr_o[i].mem_wmask <= mem_q[commit_pointer[i]].lsu_wmask;
rvfi_instr_o[i].mem_wdata <= mem_q[commit_pointer[i]].lsu_wdata;
rvfi_instr_o[i].mem_rmask <= mem_q[commit_pointer[i]].lsu_rmask;
rvfi_instr_o[i].mem_rdata <= commit_instr_result[i];
rvfi_instr_o[i].rs1_rdata <= mem_q[commit_pointer[i]].rs1_rdata;
rvfi_instr_o[i].rs2_rdata <= mem_q[commit_pointer[i]].rs2_rdata;
end
end
@ -273,17 +274,16 @@ module cva6_rvfi
// CSR
//----------------------------------------------------------------------------------------------------------
`define CONNECT_RVFI_FULL(CSR_ENABLE_COND, CSR_NAME, CSR_SOURCE_NAME) \
always_ff @(posedge clk_i) begin \
rvfi_csr_o.``CSR_NAME``.rdata = CSR_ENABLE_COND ? {{CVA6Cfg.XLEN - $bits(CSR_SOURCE_NAME)}, CSR_SOURCE_NAME} : 0; \
end \
always_comb begin \
rvfi_csr_o.``CSR_NAME``.wdata = CSR_ENABLE_COND ? { {{CVA6Cfg.XLEN-$bits(CSR_SOURCE_NAME)}, CSR_SOURCE_NAME} } : 0; \
rvfi_csr_o.``CSR_NAME``.rmask = CSR_ENABLE_COND ? 1 : 0; \
rvfi_csr_o.``CSR_NAME``.wmask = CSR_ENABLE_COND ? (rvfi_csr_o.``CSR_NAME``.rdata != {{CVA6Cfg.XLEN - $bits(CSR_SOURCE_NAME)}, CSR_SOURCE_NAME}) : 0; \
end
`define CONNECT_RVFI_FULL(CSR_ENABLE_COND, CSR_NAME,
CSR_SOURCE_NAME) \
always_ff @(posedge clk_i) begin \
if (CSR_ENABLE_COND) begin \
rvfi_csr_o.``CSR_NAME``.rdata <= {{CVA6Cfg.XLEN - $bits(CSR_SOURCE_NAME)}, CSR_SOURCE_NAME}; \
end \
end \
assign rvfi_csr_o.``CSR_NAME``.wdata = CSR_ENABLE_COND ? { {{CVA6Cfg.XLEN-$bits(CSR_SOURCE_NAME)}, CSR_SOURCE_NAME} } : 0; \
assign rvfi_csr_o.``CSR_NAME``.rmask = CSR_ENABLE_COND ? 1 : 0; \
assign rvfi_csr_o.``CSR_NAME``.wmask = (rvfi_csr_o.``CSR_NAME``.rdata != {{CVA6Cfg.XLEN - $bits(CSR_SOURCE_NAME)}, CSR_SOURCE_NAME}) && CSR_ENABLE_COND;
`define COMMA ,

80
corev_apu/tb/common/spike.sv
View file

@ -20,6 +20,9 @@
`endif
import ariane_pkg::*;
`ifndef VERILATOR
import uvm_pkg::*;
`endif
import riscv::*;
import uvma_rvfi_pkg::*;
import uvma_core_cntrl_pkg::*;
@ -62,49 +65,51 @@ module spike #(
// There is a need of delayed rvfi as the 'csr'_q signal does not have the
// written value
st_rvfi s_core, s_reference_model;
logic [63:0] pc64;
logic [31:0] rtl_instr;
logic [31:0] spike_instr;
string cause;
string instr;
st_rvfi s_core [CVA6Cfg.NrCommitPorts-1:0];
bit core_valid [CVA6Cfg.NrCommitPorts-1:0];
`define GET_RVFI_CSR(CSR_ADDR, CSR_NAME, CSR_INDEX) \
s_core[i].csr_valid[CSR_INDEX] <= 1; \
s_core[i].csr_addr [CSR_INDEX] <= CSR_ADDR;\
s_core[i].csr_rdata[CSR_INDEX] <= rvfi_csr_i.``CSR_NAME``.rdata;\
s_core[i].csr_rmask[CSR_INDEX] <= rvfi_csr_i.``CSR_NAME``.rmask;\
s_core[i].csr_wdata[CSR_INDEX] <= rvfi_csr_i.``CSR_NAME``.wdata;\
s_core[i].csr_wmask[CSR_INDEX] <= rvfi_csr_i.``CSR_NAME``.wmask;\
always_ff @(posedge clk_i) begin
if (rst_ni) begin
for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
longint unsigned index = 0;
if (rvfi_i[i].valid || rvfi_i[i].trap) begin
s_core.order = rvfi_i[i].order;
s_core.insn = rvfi_i[i].insn;
s_core.trap = rvfi_i[i].trap;
s_core.trap |= (rvfi_i[i].cause << 1);
s_core.halt = rvfi_i[i].halt;
s_core.intr = rvfi_i[i].intr;
s_core.mode = rvfi_i[i].mode;
s_core.ixl = rvfi_i[i].ixl;
s_core.rs1_addr = rvfi_i[i].rs1_addr;
s_core.rs2_addr = rvfi_i[i].rs2_addr;
s_core.rs1_rdata = rvfi_i[i].rs1_rdata;
s_core.rs2_rdata = rvfi_i[i].rs2_rdata;
s_core.rd1_addr = rvfi_i[i].rd_addr;
s_core.rd1_wdata = rvfi_i[i].rd_wdata;
s_core.pc_rdata = rvfi_i[i].pc_rdata;
s_core.pc_wdata = rvfi_i[i].pc_wdata;
s_core.mem_addr = rvfi_i[i].mem_addr;
s_core.mem_rmask = rvfi_i[i].mem_rmask;
s_core.mem_wmask = rvfi_i[i].mem_wmask;
s_core.mem_rdata = rvfi_i[i].mem_rdata;
s_core.mem_wdata = rvfi_i[i].mem_wdata;
core_valid[i] <= 1;
s_core[i].order <= rvfi_i[i].order;
s_core[i].insn <= rvfi_i[i].insn;
s_core[i].trap <= rvfi_i[i].trap;
s_core[i].trap <= (rvfi_i[i].cause << 1) | rvfi_i[i].trap[0];
s_core[i].halt <= rvfi_i[i].halt;
s_core[i].intr <= rvfi_i[i].intr;
s_core[i].mode <= rvfi_i[i].mode;
s_core[i].ixl <= rvfi_i[i].ixl;
s_core[i].rs1_addr <= rvfi_i[i].rs1_addr;
s_core[i].rs2_addr <= rvfi_i[i].rs2_addr;
s_core[i].rs1_rdata <= rvfi_i[i].rs1_rdata;
s_core[i].rs2_rdata <= rvfi_i[i].rs2_rdata;
s_core[i].rd1_addr <= rvfi_i[i].rd_addr;
s_core[i].rd1_wdata <= rvfi_i[i].rd_wdata;
s_core[i].pc_rdata <= rvfi_i[i].pc_rdata;
s_core[i].pc_wdata <= rvfi_i[i].pc_wdata;
s_core[i].mem_addr <= rvfi_i[i].mem_addr;
s_core[i].mem_rmask <= rvfi_i[i].mem_rmask;
s_core[i].mem_wmask <= rvfi_i[i].mem_wmask;
s_core[i].mem_rdata <= rvfi_i[i].mem_rdata;
s_core[i].mem_wdata <= rvfi_i[i].mem_wdata;
`define GET_RVFI_CSR(CSR_ADDR, CSR_NAME, CSR_INDEX) \
s_core.csr_valid[CSR_INDEX] = 1; \
s_core.csr_addr [CSR_INDEX] = CSR_ADDR;\
s_core.csr_rdata[CSR_INDEX] = rvfi_csr_i.``CSR_NAME``.rdata;\
s_core.csr_rmask[CSR_INDEX] = rvfi_csr_i.``CSR_NAME``.rmask;\
s_core.csr_wdata[CSR_INDEX] = rvfi_csr_i.``CSR_NAME``.wdata;\
s_core.csr_wmask[CSR_INDEX] = rvfi_csr_i.``CSR_NAME``.wmask;
`GET_RVFI_CSR (CSR_MSTATUS , mstatus , 0)
`GET_RVFI_CSR (CSR_MCAUSE , mcause , 1)
@ -126,13 +131,20 @@ module spike #(
`GET_RVFI_CSR (CSR_PMPCFG1 , pmpcfg1 , 17)
`GET_RVFI_CSR (CSR_PMPCFG2 , pmpcfg2 , 18)
`GET_RVFI_CSR (CSR_PMPCFG3 , pmpcfg3 , 19)
for (int i = 0; i < 16; i++) begin
`GET_RVFI_CSR (CSR_PMPADDR0 + i , pmpaddr[i] , 20 + i)
for (int j = 0; j < 16; j++) begin
`GET_RVFI_CSR (CSR_PMPADDR0 + j , pmpaddr[j] , 20 + j)
end
`GET_RVFI_CSR (CSR_MINSTRET , instret , 37)
end
else begin
core_valid[i] <= 0;
end
rvfi_spike_step(s_core, s_reference_model);
rvfi_compare(s_core, s_reference_model);
if (core_valid[i]) begin
st_rvfi core, reference_model;
core = s_core[i];
rvfi_spike_step(core, reference_model);
rvfi_compare(core, reference_model);
end
end
end

2
verif/sim/cva6.py
View file

@ -1056,7 +1056,7 @@ def check_gcc_version():
def check_spike_version():
# Get Spike hash from core-v-verif submodule
spike_hash = subprocess.run('git log -1 --pretty=tformat:%h -- $SPIKE_SRC_DIR/..', capture_output=True, text=True, shell=True, cwd=os.environ.get("SPIKE_SRC_DIR"))
spike_hash = subprocess.run('git log -1 --pretty=tformat:%h -- $SPIKE_SRC_DIR/', capture_output=True, text=True, shell=True, cwd=os.environ.get("SPIKE_SRC_DIR"))
spike_version = "1.1.1-dev " + spike_hash.stdout.strip()
# Get Spike User version

1
verif/tb/uvmt/uvmt_cva6_tb.sv
View file

@ -100,7 +100,6 @@ module uvmt_cva6_tb;
); // Status information generated by the Virtual Peripherals in the DUT WRAPPER memory.
uvmt_tb_exit_if tb_exit_if ( .tb_exit_o());
rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0] rvfi_instr_q;
/**
* DUT WRAPPER instance
*/