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Implement dcache bypass

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Florian Zaruba 2017-10-19 16:30:13 +02:00
parent 10f47425fb
commit 9907607901
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7 changed files with 95 additions and 49 deletions
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9
.gitmodules vendored
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@ -10,3 +10,12 @@
[submodule "tb"]
path = tb
url = ../uvm-components.git
[submodule "src/axi_mem_if"]
path = src/axi_mem_if
url = git@iis-git.ee.ethz.ch:kerbin/axi_mem_if.git
[submodule "src/axi2per"]
path = src/axi2per
url = git@iis-git.ee.ethz.ch:kerbin/axi2per.git
[submodule "src/axi_slice"]
path = src/axi_slice
url = git@iis-git.ee.ethz.ch:pulp-open/axi_slice.git

2
Makefile
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@ -27,7 +27,7 @@ test_pkg = $(wildcard tb/test/*/*sequence_pkg.sv*) $(wildcard tb/test/*/*_pkg.sv
# DPI
dpi = $(wildcard tb/dpi/*)
# this list contains the standalone components
src = $(wildcard src/*.sv) $(wildcard tb/common/*.sv)
src = $(wildcard src/*.sv) $(wildcard tb/common/*.sv) $(wildcard src/axi2per/*.sv) $(wildcard src/axi_slice/*.sv)
# look for testbenches
tbs = $(wildcard tb/*_tb.sv)
# RISCV-tests path

1
src/axi2per Submodule

@ -0,0 +1 @@
Subproject commit 04753ab7ac05f0c227599749e97bdad24ebdfc4d

2
src/axi_adapter.sv
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@ -35,7 +35,7 @@ module axi_adapter #(
input logic [AXI_ID_WIDTH-1:0] id_i,
// read port
output logic valid_o,
output logic [127:0] rdata_o,
output logic [(CACHE_LINE_WIDTH/64)-1:0] rdata_o,
output logic [AXI_ID_WIDTH-1:0] id_o,
// critical word - read port
output logic [63:0] critical_word_o,

1
src/axi_slice Submodule

@ -0,0 +1 @@
Subproject commit 940ab2b25c0d189a333343641b2e6e82ef227974

109
src/miss_handler.sv Executable file → Normal file
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@ -7,13 +7,16 @@
import nbdcache_pkg::*;
module miss_handler #(
parameter int unsigned NR_PORTS = 3
parameter int unsigned NR_PORTS = 3,
parameter int unsigned CACHE_LINE_WIDTH = 256,
parameter int unsigned AXI_ID_WIDTH = 10,
parameter int unsigned AXI_USER_WIDTH = 10
)(
input logic clk_i,
input logic rst_ni,
input logic [NR_PORTS-1:0][$bits(miss_req_t)-1:0] miss_req_i,
output logic [NR_PORTS-1:0] miss_gnt_o,
output logic [NR_PORTS-1:0] miss_valid_o,
output logic [NR_PORTS-1:0] miss_gnt_o,
output logic [NR_PORTS-1:0] miss_valid_o,
output logic [NR_PORTS-1:0][63:0] miss_data_o,
AXI_BUS.Master bypass_if
// update cache
@ -30,54 +33,86 @@ module miss_handler #(
// request from FSM
// Hack as system verilog support in modelsim seems to be buggy here
miss_req_t miss_req;
miss_req_t [NR_PORTS-1:0] miss_req;
assign miss_req = miss_req_t'(miss_req_i);
miss_req_t req_fsm_bypass;
logic gnt_bypass_fsm;
logic valid_bypass_fsm;
logic [63:0] data_bypass_fsm;
logic [$clog2(NR_PORTS)-1:0] id_bypass_fsm, id_fsm_bypass;
logic [NR_PORTS-1:0] miss_req_valid;
logic [NR_PORTS-1:0] miss_req_bypass;
logic [NR_PORTS-1:0][63:0] miss_req_addr;
logic [NR_PORTS-1:0][63:0] miss_req_wdata;
logic [NR_PORTS-1:0] miss_req_we;
logic [NR_PORTS-1:0][7:0] miss_req_be;
miss_arbiter i_bypass_arbiter (
logic req_fsm_bypass_valid;
logic req_fsm_bypass_bypass;
logic [63:0] req_fsm_bypass_addr;
logic [63:0] req_fsm_bypass_wdata;
logic req_fsm_bypass_we;
logic [7:0] req_fsm_bypass_be;
generate
for (genvar i = 0; i < NR_PORTS; i++) begin
assign miss_req_valid [i] = miss_req[i].valid;
assign miss_req_bypass [i] = miss_req[i].bypass;
assign miss_req_addr [i] = miss_req[i].addr;
assign miss_req_wdata [i] = miss_req[i].wdata;
assign miss_req_we [i] = miss_req[i].we;
assign miss_req_be [i] = miss_req[i].be;
end
endgenerate
logic gnt_bypass_fsm;
logic valid_bypass_fsm;
logic [(CACHE_LINE_WIDTH/64)-1:0] data_bypass_fsm;
logic [$clog2(NR_PORTS)-1:0] id_fsm_bypass;
logic [AXI_ID_WIDTH-1:0] id_bypass_fsm;
miss_arbiter #(
.NR_PORTS ( NR_PORTS )
) i_bypass_arbiter (
// Master Side
.data_req_i ( miss_req.valid & miss_req.bypass ),
.address_i ( miss_req.addr ),
.data_wdata_i ( miss_req.wdata ),
.data_we_i ( miss_req.we ),
.data_be_i ( miss_req.be ),
.data_req_i ( miss_req_valid & miss_req_bypass ),
.address_i ( miss_req_addr ),
.data_wdata_i ( miss_req_wdata ),
.data_we_i ( miss_req_we ),
.data_be_i ( miss_req_be ),
.data_gnt_o ( miss_gnt_o ),
.data_rvalid_o ( miss_valid_o ),
.data_rdata_o ( miss_data_o ),
// Slave Side
.id_i ( id_bypass_fsm ),
.id_i ( id_bypass_fsm[$clog2(NR_PORTS)-1:0] ),
.id_o ( id_fsm_bypass ),
.address_o ( req_fsm_bypass.addr ),
.data_wdata_o ( req_fsm_bypass.wdata ),
.data_req_o ( req_fsm_bypass.valid ),
.data_we_o ( req_fsm_bypass.we ),
.data_be_o ( req_fsm_bypass.be ),
.address_o ( req_fsm_bypass_addr ),
.data_wdata_o ( req_fsm_bypass_wdata ),
.data_req_o ( req_fsm_bypass_valid ),
.data_we_o ( req_fsm_bypass_we ),
.data_be_o ( req_fsm_bypass_be ),
.data_gnt_i ( gnt_bypass_fsm ),
.data_rvalid_i ( valid_bypass_fsm ),
.data_rdata_i ( data_bypass_fsm ),
.data_rdata_i ( data_bypass_fsm[63:0] ),
.*
);
axi_adapter i_bypass_axi_adapter (
.req_i ( miss_req.valid ),
.type_i ( SINGLE_REQ ),
.gnt_o ( gnt_bypass_fsm ),
.addr_i ( req_fsm_bypass.addr ),
.we_i ( req_fsm_bypass.we ),
.wdata_i ( req_fsm_bypass.wdata ),
.be_i ( req_fsm_bypass.be ),
.id_i ( id_fsm_bypass ),
.valid_o ( miss_valid_o ),
.rdata_o ( miss_data_o ),
.id_o ( id_bypass_fsm ),
.critical_word_o ( ), // not used for single requests
.critical_word_valid ( ), // not used for single requests
.axi ( bypass_if ),
axi_adapter #(
.CACHE_LINE_WIDTH ( CACHE_LINE_WIDTH ),
.AXI_ID_WIDTH ( AXI_ID_WIDTH ),
.AXI_USER_WIDTH ( AXI_USER_WIDTH )
) i_bypass_axi_adapter (
.req_i ( req_fsm_bypass_valid ),
.type_i ( SINGLE_REQ ),
.gnt_o ( gnt_bypass_fsm ),
.addr_i ( req_fsm_bypass_addr ),
.we_i ( req_fsm_bypass_we ),
.wdata_i ( {{{CACHE_LINE_WIDTH-64}{1'b0}}, req_fsm_bypass_wdata} ),
.be_i ( {{{CACHE_LINE_WIDTH/8-8}{1'b0}}, req_fsm_bypass_be} ),
.id_i ( {{{AXI_ID_WIDTH-$clog2(NR_PORTS)}{1'b0}}, id_fsm_bypass} ),
.valid_o ( valid_bypass_fsm ),
.rdata_o ( data_bypass_fsm ),
.id_o ( id_bypass_fsm ),
.critical_word_o ( ), // not used for single requests
.critical_word_valid ( ), // not used for single requests
.axi ( bypass_if ),
.*
);

20
src/nbdcache.sv
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@ -62,11 +62,11 @@ module nbdcache #(
logic [2:0] miss_valid;
logic [2:0][63:0] miss_data;
logic [SET_ASSOCIATIVITY-1:0] req;
logic [SET_ASSOCIATIVITY-1:0][INDEX_WIDTH-1:0] adrr;
logic [SET_ASSOCIATIVITY-1:0][CACHE_LINE_WIDTH-1:0] tag;
logic [SET_ASSOCIATIVITY-1:0][TAG_WIDTH-1:0] data;
logic [SET_ASSOCIATIVITY-1:0] we;
logic [2:0][SET_ASSOCIATIVITY-1:0] req;
logic [2:0][SET_ASSOCIATIVITY-1:0][INDEX_WIDTH-1:0] adrr;
logic [2:0][SET_ASSOCIATIVITY-1:0][CACHE_LINE_WIDTH-1:0] tag;
logic [2:0][SET_ASSOCIATIVITY-1:0][TAG_WIDTH-1:0] data;
logic [2:0][SET_ASSOCIATIVITY-1:0] we;
// ------------------
// Cache Controller
@ -93,11 +93,11 @@ module nbdcache #(
.data_rdata_o ( data_rdata_o [i] ),
.amo_op_i ( amo_op_i [i] ),
.req_o ( req ),
.adrr_o ( adrr ),
.tag_i ( tag ),
.data_i ( data ),
.we_o ( we ),
.req_o ( req [i] ),
.adrr_o ( adrr [i] ),
.tag_i ( tag [i] ),
.data_i ( data [i] ),
.we_o ( we [i] ),
.miss_req_o ( miss_req [i] ),
.miss_gnt_i ( miss_gnt [i] ),