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csr_regfile: Fix #261 non-setable MEIE bit (#302)

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Florian Zaruba 2019-08-19 15:03:16 +02:00 • committed by GitHub
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6
CHANGELOG.md
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@ -6,6 +6,12 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
## [Unreleased]
### Added
### Changed
- Fix non-setable MEIE bit in MIE CSR
### 4.2.0 - 2019-06-04
### Added

2
src/csr_regfile.sv
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@ -488,7 +488,7 @@ module csr_regfile #(
end
// mask the register so that unsupported interrupts can never be set
riscv::CSR_MIE: begin
mask = riscv::MIP_SSIP | riscv::MIP_STIP | riscv::MIP_SEIP | riscv::MIP_MSIP | riscv::MIP_MTIP;
mask = riscv::MIP_SSIP | riscv::MIP_STIP | riscv::MIP_SEIP | riscv::MIP_MSIP | riscv::MIP_MTIP | riscv::MIP_MEIP;
mie_d = (mie_q & ~mask) | (csr_wdata & mask); // we only support supervisor and M-mode interrupts
end