synthesis: Fix problems with Synopsys DC

include/ariane_pkg.sv

@@ -91,20 +91,9 @@ package ariane_pkg;
       // pragma translate_on
     endfunction
 
-    // Generate a mask for a given power of two length
-    function logic [63:0] gen_mask (input logic [63:0] len);
-      return {64{1'b1}} << $clog2(len);
-    endfunction
-
     function automatic logic range_check(logic[63:0] base, logic[63:0] len, logic[63:0] address);
       // if len is a power of two, and base is properly aligned, this chack can be simplified
-      automatic logic[63:0] mask;
-      // mask = gen_mask(len);
-      // if ((64'b1<<$clog2(len) == len) && (mask & base == base)) begin
-      //   return (address & mask) == (base & mask);
-      // end else begin
-        return (address >= base) && (address < (base+len));
-      // end
+      return (address >= base) && (address < (base+len));
     endfunction : range_check
 
     function automatic logic is_inside_nonidempotent_regions (ariane_cfg_t Cfg, logic[63:0] address);

src/cache_subsystem/wt_dcache_missunit.sv

@@ -303,7 +303,7 @@ module wt_dcache_missunit #(
 
   // cacheline write port
   assign wr_cl_nc_o      = mshr_q.nc;
-  assign wr_cl_vld_o     = load_ack | |wr_cl_we_o;
+  assign wr_cl_vld_o     = load_ack | (| wr_cl_we_o);
 
   assign wr_cl_we_o      = (flush_en   )  ? '1                                    :
                            (inv_vld_all)   ? '1                                    :
@@ -536,4 +536,4 @@ end
 `endif
 //pragma translate_on
 
-endmodule // wt_dcache_missunit
+endmodule // wt_dcache_missunit

src/csr_regfile.sv

@@ -97,24 +97,14 @@ module csr_regfile #(
     logic  dret;  // return from debug mode
     // CSR write causes us to mark the FPU state as dirty
     logic  dirty_fp_state_csr;
+    riscv::status_rv64_t  mstatus_q,  mstatus_d;
+    riscv::satp_t         satp_q, satp_d;
+    riscv::dcsr_t         dcsr_q,     dcsr_d;
     riscv::csr_t  csr_addr;
-    // ----------------
-    // Assignments
-    // ----------------
-    assign csr_addr = riscv::csr_t'(csr_addr_i);
-    assign fs_o = mstatus_q.fs;
-    // ----------------
-    // CSR Registers
-    // ----------------
     // privilege level register
     riscv::priv_lvl_t   priv_lvl_d, priv_lvl_q;
     // we are in debug
     logic        debug_mode_q, debug_mode_d;
-
-    riscv::status_rv64_t  mstatus_q,  mstatus_d;
-    riscv::satp_t         satp_q, satp_d;
-    riscv::dcsr_t         dcsr_q,     dcsr_d;
-
     logic        mtvec_rst_load_q;// used to determine whether we came out of reset
 
     logic [63:0] dpc_q,       dpc_d;
@@ -144,7 +134,11 @@ module csr_regfile #(
     logic [63:0] instret_q,   instret_d;
 
     riscv::fcsr_t fcsr_q, fcsr_d;
-
+    // ----------------
+    // Assignments
+    // ----------------
+    assign csr_addr = riscv::csr_t'(csr_addr_i);
+    assign fs_o = mstatus_q.fs;
     // ----------------
     // CSR Read logic
     // ----------------

src/fpu_wrap.sv

@@ -34,9 +34,7 @@ module fpu_wrap (
 
 // this is a workaround
 // otherwise compilation might issue an error if FLEN=0
-generate
   if (FP_PRESENT) begin : fpu_gen
-
     logic [FLEN-1:0] operand_a_i;
     logic [FLEN-1:0] operand_b_i;
     logic [FLEN-1:0] operand_c_i;
@@ -550,5 +548,4 @@ generate
     assign fpu_valid_o = fpu_out_valid;
 
   end
-endgenerate
 endmodule

src/frontend/instr_scan.sv

@@ -48,7 +48,7 @@ module instr_scan (
     assign rvc_jump_o   = (instr_i[15:13] == riscv::OpcodeC1J) & is_rvc & (instr_i[1:0] == riscv::OpcodeC1);
     // always links to register 0
     logic is_jal_r;
-    assign is_jal_r     = (instr_i[15:13] == riscv::OpcodeC2JalrMvAdd) &
+    assign is_jal_r     = (instr_i[15:13] == riscv::OpcodeC2JalrMvAdd)
                         & (instr_i[6:2] == 5'b00000)
                         & (instr_i[1:0] == riscv::OpcodeC2)
                         & is_rvc;