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Register stage between decode and issue

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This commit is contained in:
Florian Zaruba 2017-06-21 16:49:32 +02:00
parent 332c048b8a
commit a924dc96f4
2 changed files with 33 additions and 15 deletions
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10
src/fetch_fifo.sv
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@ -143,7 +143,7 @@ module fetch_fifo
// check if the instruction is compressed
if (in_rdata_q[1:0] != 2'b11) begin
// it is compressed
mem_n[write_pointer_q] = {
mem_n[write_pointer_q] = {
branch_predict_q, ex_q, in_addr_q, decompressed_instruction[0], 1'b1, is_illegal[0]
};
@ -158,7 +158,7 @@ module fetch_fifo
// but only if we predicted it to be taken, the predict was on the lower 16 bit compressed instruction
if (in_rdata_q[17:16] != 2'b11 && !(branch_predict_q.valid && branch_predict_q.predict_taken && branch_predict_q.is_lower_16)) begin
mem_n[write_pointer_q + 1'b1] = {
mem_n[write_pointer_q + 1'b1] = {
branch_predict_q, ex_q, {in_addr_q[63:2], 2'b10}, decompressed_instruction[1], 1'b1, is_illegal[1]
};
@ -195,12 +195,6 @@ module fetch_fifo
mem_n[write_pointer_q] = {
branch_predict_q, ex_q, unaligned_address_q, {in_rdata_q[15:0], unaligned_instr_q}, 1'b0, 1'b0
};
// // check if we predicted on the unaligned instruction part
// if (!branch_predict_q.is_lower_16) begin
// // only output branch prediction here if we indeed meant it, e.g.: null it if it is not on the
// // lower 16 bit. Because then it would be valid for the upper part
// mem_n[write_pointer_q].branch_predict.valid = 1'b0;
// end
status_cnt++;
write_pointer++;

38
src/scoreboard.sv
View file

@ -76,6 +76,13 @@ module scoreboard #(
logic [$clog2(NR_ENTRIES)-1:0] commit_pointer_n, commit_pointer_q;
logic issue_full;
struct packed {
logic valid;
scoreboard_entry sbe;
} decoded_instr_n, decoded_instr_q;
logic decoded_instr_ack;
// the issue queue is full don't issue any new instructions
assign issue_full = (issue_cnt_q == NR_ENTRIES-1);
assign full_o = issue_full;
@ -84,11 +91,28 @@ module scoreboard #(
// an instruction is ready for issue if we have place in the issue FIFO and it the decoder says it is valid
always_comb begin
issue_instr_o = decoded_instr_i;
issue_instr_o = decoded_instr_q;
// make sure we assign the correct trans ID
issue_instr_o.trans_id = issue_pointer_q;
issue_instr_valid_o = !issue_full && decoded_instr_valid_i;
decoded_instr_ack_o = issue_ack_i;
issue_instr_valid_o = decoded_instr_q.valid;
decoded_instr_ack_o = decoded_instr_ack;
end
always_comb begin : decode_if
decoded_instr_ack = 1'b0;
decoded_instr_n = decoded_instr_q;
if (issue_ack_i)
decoded_instr_n.valid = 1'b0;
if (!decoded_instr_q.valid && decoded_instr_valid_i) begin
decoded_instr_ack = 1'b1;
decoded_instr_n = {1'b1, decoded_instr_i};
end
if (decoded_instr_q.valid && !issue_full && issue_ack_i) begin
decoded_instr_ack = 1'b1;
decoded_instr_n = {1'b1, decoded_instr_i};
end
end
// maintain a FIFO with issued instructions
// keep track of all issued instructions
@ -99,14 +123,12 @@ module scoreboard #(
commit_pointer_n = commit_pointer_q;
issue_pointer_n = issue_pointer_q;
// if we got a acknowledge from the issue stage, put this scoreboard entry in the queue
if (issue_ack_i) begin
// the decoded instruction we put in there is valid (1st bit)
mem_n[issue_pointer_q] = {1'b1, decoded_instr_i};
// increase the issue counter
issue_cnt++;
mem_n[issue_pointer_q].issued = 1'b1;
mem_n[issue_pointer_q] = {1'b1, decoded_instr_i};
// advance issue pointer
issue_pointer_n = issue_pointer_q + 1'b1;
end
@ -232,11 +254,13 @@ module scoreboard #(
issue_cnt_q <= '0;
commit_pointer_q <= '0;
issue_pointer_q <= '0;
decoded_instr_q <= '0;
end else begin
mem_q <= mem_n;
mem_q <= mem_n;
issue_cnt_q <= issue_cnt_n;
commit_pointer_q <= commit_pointer_n;
issue_pointer_q <= issue_pointer_n;
decoded_instr_q <= decoded_instr_n;
end
end
`ifndef SYNTHESIS