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🎨 Beautify code, fix #26

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This commit is contained in:
Florian Zaruba 2017-06-19 11:04:54 +02:00
parent 975ef03f81
commit ab71983328
10 changed files with 227 additions and 239 deletions
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40
include/ariane_pkg.svh
View file

@ -217,27 +217,27 @@ package ariane_pkg;
// ----------------------
// Exception Cause Codes
// ----------------------
localparam logic [63:0] INSTR_ADDR_MISALIGNED = 64'd0;
localparam logic [63:0] INSTR_ACCESS_FAULT = 64'd1;
localparam logic [63:0] ILLEGAL_INSTR = 64'd2;
localparam logic [63:0] BREAKPOINT = 64'd3;
localparam logic [63:0] LD_ADDR_MISALIGNED = 64'd4;
localparam logic [63:0] LD_ACCESS_FAULT = 64'd5;
localparam logic [63:0] ST_ADDR_MISALIGNED = 64'd6;
localparam logic [63:0] ST_ACCESS_FAULT = 64'd7;
localparam logic [63:0] ENV_CALL_UMODE = 64'd8; // environment call from user mode
localparam logic [63:0] ENV_CALL_SMODE = 64'd9; // environment call from supervisor mode
localparam logic [63:0] ENV_CALL_MMODE = 64'd11; // environment call from machine mode
localparam logic [63:0] INSTR_PAGE_FAULT = 64'd12; // Instruction page fault
localparam logic [63:0] LOAD_PAGE_FAULT = 64'd13; // Load page fault
localparam logic [63:0] STORE_PAGE_FAULT = 64'd15; // Store page fault
localparam logic [63:0] INSTR_ADDR_MISALIGNED = 0;
localparam logic [63:0] INSTR_ACCESS_FAULT = 1;
localparam logic [63:0] ILLEGAL_INSTR = 2;
localparam logic [63:0] BREAKPOINT = 3;
localparam logic [63:0] LD_ADDR_MISALIGNED = 4;
localparam logic [63:0] LD_ACCESS_FAULT = 5;
localparam logic [63:0] ST_ADDR_MISALIGNED = 6;
localparam logic [63:0] ST_ACCESS_FAULT = 7;
localparam logic [63:0] ENV_CALL_UMODE = 8; // environment call from user mode
localparam logic [63:0] ENV_CALL_SMODE = 9; // environment call from supervisor mode
localparam logic [63:0] ENV_CALL_MMODE = 11; // environment call from machine mode
localparam logic [63:0] INSTR_PAGE_FAULT = 12; // Instruction page fault
localparam logic [63:0] LOAD_PAGE_FAULT = 13; // Load page fault
localparam logic [63:0] STORE_PAGE_FAULT = 15; // Store page fault
localparam logic [63:0] S_SW_INTERRUPT = (1 << 63) | 64'd1;
localparam logic [63:0] M_SW_INTERRUPT = (1 << 63) | 64'd3;
localparam logic [63:0] S_TIMER_INTERRUPT = (1 << 63) | 64'd5;
localparam logic [63:0] M_TIMER_INTERRUPT = (1 << 63) | 64'd7;
localparam logic [63:0] S_EXT_INTERRUPT = (1 << 63) | 64'd9;
localparam logic [63:0] M_EXT_INTERRUPT = (1 << 63) | 64'd11;
localparam logic [63:0] S_SW_INTERRUPT = (1 << 63) | 1;
localparam logic [63:0] M_SW_INTERRUPT = (1 << 63) | 3;
localparam logic [63:0] S_TIMER_INTERRUPT = (1 << 63) | 5;
localparam logic [63:0] M_TIMER_INTERRUPT = (1 << 63) | 7;
localparam logic [63:0] S_EXT_INTERRUPT = (1 << 63) | 9;
localparam logic [63:0] M_EXT_INTERRUPT = (1 << 63) | 11;
// -----
// CSRs
// -----

4
src/alu.sv
View file

@ -123,9 +123,9 @@ module alu
assign shift_op_a_64 = { shift_arithmetic & shift_op_a[63], shift_op_a};
assign shift_op_a_32 = { shift_arithmetic & shift_op_a[31], shift_op_a32};
assign shift_right_result = $signed(shift_op_a_64) >>> shift_amt[5:0];
assign shift_right_result = $unsigned($signed(shift_op_a_64) >>> shift_amt[5:0]);
assign shift_right_result32 = $signed(shift_op_a_32) >>> shift_amt[4:0];
assign shift_right_result32 = $unsigned($signed(shift_op_a_32) >>> shift_amt[4:0]);
// bit reverse the shift_right_result for left shifts
genvar j;
generate

382
src/compressed_decoder.sv
View file

@ -32,226 +32,222 @@ module compressed_decoder
output logic illegal_instr_o
);
// -------------------
// Compressed Decoder
// -------------------
always_comb begin
illegal_instr_o = 1'b0;
instr_o = '0;
// -------------------
// Compressed Decoder
// -------------------
always_comb begin
illegal_instr_o = 1'b0;
instr_o = '0;
unique case (instr_i[1:0])
// C0
2'b00: begin
unique case (instr_i[15:13])
3'b000: begin
// c.addi4spn -> addi rd', x2, imm
instr_o = {2'b0, instr_i[10:7], instr_i[12:11], instr_i[5], instr_i[6], 2'b00, 5'h02, 3'b000, 2'b01, instr_i[4:2], OPCODE_OPIMM};
if (instr_i[12:5] == 8'b0) illegal_instr_o = 1'b1;
end
unique case (instr_i[1:0])
// C0
2'b00: begin
unique case (instr_i[15:13])
3'b000: begin
// c.addi4spn -> addi rd', x2, imm
instr_o = {2'b0, instr_i[10:7], instr_i[12:11], instr_i[5], instr_i[6], 2'b00, 5'h02, 3'b000, 2'b01, instr_i[4:2], OPCODE_OPIMM};
if (instr_i[12:5] == 8'b0) illegal_instr_o = 1'b1;
end
3'b010: begin
// c.lw -> lw rd', imm(rs1')
instr_o = {5'b0, instr_i[5], instr_i[12:10], instr_i[6], 2'b00, 2'b01, instr_i[9:7], 3'b010, 2'b01, instr_i[4:2], OPCODE_LOAD};
end
3'b010: begin
// c.lw -> lw rd', imm(rs1')
instr_o = {5'b0, instr_i[5], instr_i[12:10], instr_i[6], 2'b00, 2'b01, instr_i[9:7], 3'b010, 2'b01, instr_i[4:2], OPCODE_LOAD};
end
3'b011: begin
// c.ld -> ld rd', imm(rs1')
// | imm[11:0] | rs1 | funct3 | rd | opcode |
instr_o = {4'b0, instr_i[6:5], instr_i[12:10], 3'b000, 2'b01, instr_i[9:7], 3'b011, 2'b01, instr_i[4:2], OPCODE_LOAD};
end
3'b011: begin
// c.ld -> ld rd', imm(rs1')
// | imm[11:0] | rs1 | funct3 | rd | opcode |
instr_o = {4'b0, instr_i[6:5], instr_i[12:10], 3'b000, 2'b01, instr_i[9:7], 3'b011, 2'b01, instr_i[4:2], OPCODE_LOAD};
end
3'b110: begin
// c.sw -> sw rs2', imm(rs1')
instr_o = {5'b0, instr_i[5], instr_i[12], 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b010, instr_i[11:10], instr_i[6], 2'b00, OPCODE_STORE};
end
3'b110: begin
// c.sw -> sw rs2', imm(rs1')
instr_o = {5'b0, instr_i[5], instr_i[12], 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b010, instr_i[11:10], instr_i[6], 2'b00, OPCODE_STORE};
end
3'b111: begin
// c.sd -> sd rs2', imm(rs1')
instr_o = {4'b0, instr_i[6:5], instr_i[12], 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b011, instr_i[11:10], 3'b000, OPCODE_STORE};
end
3'b111: begin
// c.sd -> sd rs2', imm(rs1')
instr_o = {4'b0, instr_i[6:5], instr_i[12], 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b011, instr_i[11:10], 3'b000, OPCODE_STORE};
end
default: begin
illegal_instr_o = 1'b1;
end
endcase
end
// C1
2'b01: begin
unique case (instr_i[15:13])
3'b000: begin
// c.addi -> addi rd, rd, nzimm
// c.nop -> addi 0, 0, 0
instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], instr_i[11:7], 3'b0, instr_i[11:7], OPCODE_OPIMM};
end
// c.addiw -> addiw rd, rd, nzimm for RV64
3'b001: begin
if (instr_i[11:7] != 5'h0) // only valid if the destination is not r0
instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], instr_i[11:7], 3'b0, instr_i[11:7], OPCODE_OPIMM32};
else
illegal_instr_o = 1'b1;
end
3'b101: begin
// 101: c.j -> jal x0, imm
instr_o = {instr_i[12], instr_i[8], instr_i[10:9], instr_i[6], instr_i[7], instr_i[2], instr_i[11], instr_i[5:3], {9 {instr_i[12]}}, 4'b0, ~instr_i[15], OPCODE_JAL};
end
3'b010: begin
// c.li -> addi rd, x0, nzimm
instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], 5'b0, 3'b0, instr_i[11:7], OPCODE_OPIMM};
if (instr_i[11:7] == 5'b0) illegal_instr_o = 1'b1;
end
3'b011: begin
// c.lui -> lui rd, imm
instr_o = {{15 {instr_i[12]}}, instr_i[6:2], instr_i[11:7], OPCODE_LUI};
if (instr_i[11:7] == 5'h02) begin
// c.addi16sp -> addi x2, x2, nzimm
instr_o = {{3 {instr_i[12]}}, instr_i[4:3], instr_i[5], instr_i[2], instr_i[6], 4'b0, 5'h02, 3'b000, 5'h02, OPCODE_OPIMM};
end else if (instr_i[11:7] == 5'b0) begin
illegal_instr_o = 1'b1;
default: begin
illegal_instr_o = 1'b1;
end
endcase
end
if ({instr_i[12], instr_i[6:2]} == 6'b0) illegal_instr_o = 1'b1;
end
3'b100: begin
unique case (instr_i[11:10])
2'b00,
2'b01: begin
// 00: c.srli -> srli rd, rd, shamt
// 01: c.srai -> srai rd, rd, shamt
instr_o = {1'b0, instr_i[10], 5'b0, instr_i[6:2], 2'b01, instr_i[9:7], 3'b101, 2'b01, instr_i[9:7], OPCODE_OPIMM};
if (instr_i[6:2] == 5'b0) illegal_instr_o = 1'b1;
end
2'b10: begin
// c.andi -> andi rd, rd, imm
instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], 2'b01, instr_i[9:7], 3'b111, 2'b01, instr_i[9:7], OPCODE_OPIMM};
end
2'b11: begin
unique case ({instr_i[12], instr_i[6:5]})
// C1
2'b01: begin
unique case (instr_i[15:13])
3'b000: begin
// c.sub -> sub rd', rd', rs2'
instr_o = {2'b01, 5'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b000, 2'b01, instr_i[9:7], OPCODE_OP};
// c.addi -> addi rd, rd, nzimm
// c.nop -> addi 0, 0, 0
instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], instr_i[11:7], 3'b0, instr_i[11:7], OPCODE_OPIMM};
end
// c.addiw -> addiw rd, rd, nzimm for RV64
3'b001: begin
// c.xor -> xor rd', rd', rs2'
instr_o = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b100, 2'b01, instr_i[9:7], OPCODE_OP};
if (instr_i[11:7] != 5'h0) // only valid if the destination is not r0
instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], instr_i[11:7], 3'b0, instr_i[11:7], OPCODE_OPIMM32};
else
illegal_instr_o = 1'b1;
end
3'b101: begin
// 101: c.j -> jal x0, imm
instr_o = {instr_i[12], instr_i[8], instr_i[10:9], instr_i[6], instr_i[7], instr_i[2], instr_i[11], instr_i[5:3], {9 {instr_i[12]}}, 4'b0, ~instr_i[15], OPCODE_JAL};
end
3'b010: begin
// c.or -> or rd', rd', rs2'
instr_o = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b110, 2'b01, instr_i[9:7], OPCODE_OP};
// c.li -> addi rd, x0, nzimm
instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], 5'b0, 3'b0, instr_i[11:7], OPCODE_OPIMM};
if (instr_i[11:7] == 5'b0) illegal_instr_o = 1'b1;
end
3'b011: begin
// c.and -> and rd', rd', rs2'
instr_o = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b111, 2'b01, instr_i[9:7], OPCODE_OP};
// c.lui -> lui rd, imm
instr_o = {{15 {instr_i[12]}}, instr_i[6:2], instr_i[11:7], OPCODE_LUI};
if (instr_i[11:7] == 5'h02) begin
// c.addi16sp -> addi x2, x2, nzimm
instr_o = {{3 {instr_i[12]}}, instr_i[4:3], instr_i[5], instr_i[2], instr_i[6], 4'b0, 5'h02, 3'b000, 5'h02, OPCODE_OPIMM};
end else if (instr_i[11:7] == 5'b0) begin
illegal_instr_o = 1'b1;
end
if ({instr_i[12], instr_i[6:2]} == 6'b0) illegal_instr_o = 1'b1;
end
3'b100: begin
// c.subw -> subw rd', rd', rs2'
instr_o = {2'b01, 5'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b000, 2'b01, instr_i[9:7], OPCODE_OP32};
end
3'b101: begin
// c.addw -> addw rd', rd', rs2'
instr_o = {2'b00, 5'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b000, 2'b01, instr_i[9:7], OPCODE_OP32};
unique case (instr_i[11:10])
2'b00,
2'b01: begin
// 00: c.srli -> srli rd, rd, shamt
// 01: c.srai -> srai rd, rd, shamt
instr_o = {1'b0, instr_i[10], 5'b0, instr_i[6:2], 2'b01, instr_i[9:7], 3'b101, 2'b01, instr_i[9:7], OPCODE_OPIMM};
if (instr_i[6:2] == 5'b0) illegal_instr_o = 1'b1;
end
2'b10: begin
// c.andi -> andi rd, rd, imm
instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], 2'b01, instr_i[9:7], 3'b111, 2'b01, instr_i[9:7], OPCODE_OPIMM};
end
2'b11: begin
unique case ({instr_i[12], instr_i[6:5]})
3'b000: begin
// c.sub -> sub rd', rd', rs2'
instr_o = {2'b01, 5'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b000, 2'b01, instr_i[9:7], OPCODE_OP};
end
3'b001: begin
// c.xor -> xor rd', rd', rs2'
instr_o = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b100, 2'b01, instr_i[9:7], OPCODE_OP};
end
3'b010: begin
// c.or -> or rd', rd', rs2'
instr_o = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b110, 2'b01, instr_i[9:7], OPCODE_OP};
end
3'b011: begin
// c.and -> and rd', rd', rs2'
instr_o = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b111, 2'b01, instr_i[9:7], OPCODE_OP};
end
3'b100: begin
// c.subw -> subw rd', rd', rs2'
instr_o = {2'b01, 5'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b000, 2'b01, instr_i[9:7], OPCODE_OP32};
end
3'b101: begin
// c.addw -> addw rd', rd', rs2'
instr_o = {2'b00, 5'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b000, 2'b01, instr_i[9:7], OPCODE_OP32};
end
3'b110,
3'b111: begin
// 100: c.subw
// 101: c.addw
illegal_instr_o = 1'b1;
instr_o = {16'b0, instr_i};
end
endcase
end
endcase
end
3'b110,
3'b111: begin
// 100: c.subw
// 101: c.addw
illegal_instr_o = 1'b1;
instr_o = {16'b0, instr_i};
3'b110, 3'b111: begin
// 0: c.beqz -> beq rs1', x0, imm
// 1: c.bnez -> bne rs1', x0, imm
instr_o = {{4 {instr_i[12]}}, instr_i[6:5], instr_i[2], 5'b0, 2'b01, instr_i[9:7], 2'b00, instr_i[13], instr_i[11:10], instr_i[4:3], instr_i[12], OPCODE_BRANCH};
end
endcase
end
endcase
end
3'b110, 3'b111: begin
// 0: c.beqz -> beq rs1', x0, imm
// 1: c.bnez -> bne rs1', x0, imm
instr_o = {{4 {instr_i[12]}}, instr_i[6:5], instr_i[2], 5'b0, 2'b01, instr_i[9:7], 2'b00, instr_i[13], instr_i[11:10], instr_i[4:3], instr_i[12], OPCODE_BRANCH};
end
default: begin
illegal_instr_o = 1'b1;
end
endcase
end
// C2
2'b10: begin
unique case (instr_i[15:13])
3'b000: begin
// c.slli -> slli rd, rd, shamt
instr_o = {7'b0, instr_i[6:2], instr_i[11:7], 3'b001, instr_i[11:7], OPCODE_OPIMM};
if (instr_i[11:7] == 5'b0) illegal_instr_o = 1'b1; // register not x0
if (instr_i[6:2] == 5'b0) illegal_instr_o = 1'b1; // shift amount must be non zero
end
3'b010: begin
// c.lwsp -> lw rd, imm(x2)
instr_o = {4'b0, instr_i[3:2], instr_i[12], instr_i[6:4], 2'b00, 5'h02, 3'b010, instr_i[11:7], OPCODE_LOAD};
if (instr_i[11:7] == 5'b0) illegal_instr_o = 1'b1;
end
3'b011: begin
// c.ldsp -> ld rd, imm(x2)
instr_o = {3'b0, instr_i[4:2], instr_i[12], instr_i[6:5], 3'b000, 5'h02, 3'b011, instr_i[11:7], OPCODE_LOAD};
if (instr_i[11:7] == 5'b0) illegal_instr_o = 1'b1;
end
3'b100: begin
if (instr_i[12] == 1'b0) begin
// c.mv -> add rd/rs1, x0, rs2
instr_o = {7'b0, instr_i[6:2], 5'b0, 3'b0, instr_i[11:7], OPCODE_OP};
if (instr_i[6:2] == 5'b0) begin
// c.jr -> jalr x0, rd/rs1, 0
instr_o = {12'b0, instr_i[11:7], 3'b0, 5'b0, OPCODE_JALR};
end
end else begin
// c.add -> add rd, rd, rs2
instr_o = {7'b0, instr_i[6:2], instr_i[11:7], 3'b0, instr_i[11:7], OPCODE_OP};
if (instr_i[11:7] == 5'b0) begin
// c.ebreak -> ebreak
instr_o = {32'h00_10_00_73};
if (instr_i[6:2] != 5'b0)
illegal_instr_o = 1'b1;
end else if (instr_i[6:2] == 5'b0) begin
// c.jalr -> jalr x1, rs1, 0
instr_o = {12'b0, instr_i[11:7], 3'b000, 5'b00001, OPCODE_JALR};
end
endcase
end
end
3'b110: begin
// c.swsp -> sw rs2, imm(x2)
instr_o = {4'b0, instr_i[8:7], instr_i[12], instr_i[6:2], 5'h02, 3'b010, instr_i[11:9], 2'b00, OPCODE_STORE};
end
// C2
2'b10: begin
unique case (instr_i[15:13])
3'b000: begin
// c.slli -> slli rd, rd, shamt
instr_o = {7'b0, instr_i[6:2], instr_i[11:7], 3'b001, instr_i[11:7], OPCODE_OPIMM};
if (instr_i[11:7] == 5'b0) illegal_instr_o = 1'b1; // register not x0
if (instr_i[6:2] == 5'b0) illegal_instr_o = 1'b1; // shift amount must be non zero
end
3'b111: begin
// c.sdsp -> sd rs2, imm(x2)
instr_o = {3'b0, instr_i[9:7], instr_i[12], instr_i[6:2], 5'h02, 3'b011, instr_i[11:10], 3'b000, OPCODE_STORE};
end
3'b010: begin
// c.lwsp -> lw rd, imm(x2)
instr_o = {4'b0, instr_i[3:2], instr_i[12], instr_i[6:4], 2'b00, 5'h02, 3'b010, instr_i[11:7], OPCODE_LOAD};
if (instr_i[11:7] == 5'b0) illegal_instr_o = 1'b1;
end
default: begin
illegal_instr_o = 1'b1;
end
3'b011: begin
// c.ldsp -> ld rd, imm(x2)
instr_o = {3'b0, instr_i[4:2], instr_i[12], instr_i[6:5], 3'b000, 5'h02, 3'b011, instr_i[11:7], OPCODE_LOAD};
if (instr_i[11:7] == 5'b0) illegal_instr_o = 1'b1;
end
3'b100: begin
if (instr_i[12] == 1'b0) begin
// c.mv -> add rd/rs1, x0, rs2
instr_o = {7'b0, instr_i[6:2], 5'b0, 3'b0, instr_i[11:7], OPCODE_OP};
if (instr_i[6:2] == 5'b0) begin
// c.jr -> jalr x0, rd/rs1, 0
instr_o = {12'b0, instr_i[11:7], 3'b0, 5'b0, OPCODE_JALR};
end
end else begin
// c.add -> add rd, rd, rs2
instr_o = {7'b0, instr_i[6:2], instr_i[11:7], 3'b0, instr_i[11:7], OPCODE_OP};
if (instr_i[11:7] == 5'b0) begin
// c.ebreak -> ebreak
instr_o = {32'h00_10_00_73};
if (instr_i[6:2] != 5'b0)
illegal_instr_o = 1'b1;
end else if (instr_i[6:2] == 5'b0) begin
// c.jalr -> jalr x1, rs1, 0
instr_o = {12'b0, instr_i[11:7], 3'b000, 5'b00001, OPCODE_JALR};
end
end
end
3'b110: begin
// c.swsp -> sw rs2, imm(x2)
instr_o = {4'b0, instr_i[8:7], instr_i[12], instr_i[6:2], 5'h02, 3'b010, instr_i[11:9], 2'b00, OPCODE_STORE};
end
3'b111: begin
// c.sdsp -> sd rs2, imm(x2)
instr_o = {3'b0, instr_i[9:7], instr_i[12], instr_i[6:2], 5'h02, 3'b011, instr_i[11:10], 3'b000, OPCODE_STORE};
end
default: begin
illegal_instr_o = 1'b1;
end
endcase
end
default: ;
endcase
end
default: ;
endcase
end
end
endmodule

9
src/csr_regfile.sv
View file

@ -79,11 +79,7 @@ module csr_regfile #(
priv_lvl_t trap_to_priv_lvl;
// register for enabling load store address translation, this is critical, hence the register
logic en_ld_st_translation_n, en_ld_st_translation_q;
// ----------------------
// LD/ST Privilege Level
// ----------------------
assign ld_st_priv_lvl_o = (mstatus_q.mprv) ? mstatus_q.mpp : priv_lvl_o;
assign en_ld_st_translation_o = en_ld_st_translation_q;
// ----------------
// CSR Registers
// ----------------
@ -362,6 +358,9 @@ module csr_regfile #(
en_ld_st_translation_n = 1'b1;
else // otherwise we go with the regular settings
en_ld_st_translation_n = en_translation_o;
ld_st_priv_lvl_o = (mstatus_q.mprv) ? mstatus_q.mpp : priv_lvl_o;
en_ld_st_translation_o = en_ld_st_translation_q;
// -----------------------
// Return from Exception
// -----------------------

2
src/decoder.sv
View file

@ -276,8 +276,6 @@ module decoder (
else
illegal_instr = 1'b1;
end
default: illegal_instr = 1'b1;
endcase
end

2
src/fetch_fifo.sv
View file

@ -40,7 +40,7 @@ module fetch_fifo
input logic out_ready_i
);
localparam DEPTH = 8; // must be a power of two
localparam int unsigned DEPTH = 8; // must be a power of two
// input registers - bounding the path from memory
branchpredict_sbe branch_predict_n, branch_predict_q;

7
src/if_stage.sv
View file

@ -88,7 +88,7 @@ module if_stage (
NS = CS;
addr_valid = 1'b0;
unique case(CS)
case(CS)
// default state, not waiting for requested data
IDLE: begin
instr_addr_o = fetch_address;
@ -211,11 +211,6 @@ module if_stage (
// otherwise wait in this state for the rvalid
end
end
default: begin
NS = IDLE;
instr_req_o = 1'b0;
end
endcase
end

2
src/lsu.sv
View file

@ -108,7 +108,7 @@ module lsu #(
logic [63:0] vaddr_i;
logic [7:0] be_i;
assign vaddr_i = $signed(imm_i) + $signed(operand_a_i);
assign vaddr_i = $unsigned($signed(imm_i) + $signed(operand_a_i));
logic st_valid_i;
logic st_ready_o;

2
src/pcgen.sv
View file

@ -49,7 +49,7 @@ module pcgen (
assign fetch_address_o = npc_q;
btb #(
.NR_ENTRIES(4096),
.NR_ENTRIES(64),
.BITS_SATURATION_COUNTER(2)
)
btb_i

16
src/scoreboard.sv
View file

@ -21,8 +21,8 @@
import ariane_pkg::*;
module scoreboard #(
parameter int NR_ENTRIES = 8,
parameter int NR_WB_PORTS = 1
parameter int unsigned NR_ENTRIES = 8,
parameter int unsigned NR_WB_PORTS = 1
)
(
input logic clk_i, // Clock
@ -63,7 +63,7 @@ module scoreboard #(
input exception [NR_WB_PORTS-1:0] ex_i, // exception from a functional unit (e.g.: ld/st exception, divide by zero)
input logic [NR_WB_PORTS-1:0] wb_valid_i // data in is valid
);
localparam BITS_ENTRIES = $clog2(NR_ENTRIES);
localparam int unsigned BITS_ENTRIES = $clog2(NR_ENTRIES);
// this is the FIFO struct of the issue queue
struct packed {
@ -112,7 +112,7 @@ module scoreboard #(
// ------------
// Write Back
// ------------
for (int i = 0; i < NR_WB_PORTS; i++) begin
for (int unsigned i = 0; i < NR_WB_PORTS; i++) begin
// check if this instruction was issued (e.g.: it could happen after a flush that there is still
// something in the pipeline e.g. an incomplete memory operation)
if (wb_valid_i[i] && mem_n[trans_id_i[i]].issued) begin
@ -141,7 +141,7 @@ module scoreboard #(
// Flush
// ------
if (flush_i) begin
for (int i = 0; i < NR_ENTRIES; i++) begin
for (int unsigned i = 0; i < NR_ENTRIES; i++) begin
// set all valid flags for all entries to zero
mem_n[i].issued = 1'b0;
mem_n[i].sbe.valid = 1'b0;
@ -163,7 +163,7 @@ module scoreboard #(
always_comb begin : clobber_output
rd_clobber_o = '{default: NONE};
// check for all valid entries and set the clobber register accordingly
for (int i = 0; i < NR_ENTRIES; i++) begin
for (int unsigned i = 0; i < NR_ENTRIES; i++) begin
if (mem_q[i].issued) begin
// output the functional unit which is going to clobber this register
rd_clobber_o[mem_q[i].sbe.rd] = mem_q[i].sbe.fu;
@ -183,7 +183,7 @@ module scoreboard #(
rs1_valid_o = 1'b0;
rs2_valid_o = 1'b0;
for (int i = 0; i < NR_ENTRIES; i++) begin
for (int unsigned i = 0; i < NR_ENTRIES; i++) begin
// only consider this entry if it is valid
if (mem_q[i].issued) begin
// look at the appropriate fields and look whether there was an
@ -203,7 +203,7 @@ module scoreboard #(
// -----------
// provide a direct combinational path from WB a.k.a forwarding
// make sure that we are not forwarding a result that got an exception
for (int j = 0; j < NR_WB_PORTS; j++) begin
for (int unsigned j = 0; j < NR_WB_PORTS; j++) begin
if (mem_q[trans_id_i[j]].sbe.rd == rs1_i && wb_valid_i[j] && ~ex_i[j].valid) begin
rs1_o = wdata_i[j];
rs1_valid_o = wb_valid_i[j];