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https://github.com/openhwgroup/cva6.git
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Instantiated CSR File and wiring control
This commit is contained in:
Florian Zaruba
parent
556a78bf9c
commit
b0040c754d
6 changed files with 101 additions and 34 deletions
9
Makefile
9
Makefile
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@ -32,7 +32,8 @@ test_case = alu_test
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# QuestaSim Version
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questa_version = -10.5c
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compile_flag = +cover=bcfst+/dut
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# Moore binary
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moore = ~fschuiki/bin/moore
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# Iterate over all include directories and write them with +incdir+ prefixed
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# +incdir+ works for Verilator and QuestaSim
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list_incdir = $(foreach dir, ${incdir}, +incdir+$(dir))
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@ -70,6 +71,10 @@ $(tests):
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# vsim${questa_version} +UVM_TESTNAME=$@_test -coverage -classdebug $@_tb_optimized
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vsim${questa_version} +UVM_TESTNAME=$@_test +uvm_set_action="*,_ALL_,UVM_ERROR,UVM_DISPLAY|UVM_STOP" -c -coverage -classdebug -do "coverage save -onexit $@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" $@_tb_optimized
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build-moore:
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# $(moore) compile src/fifo.sv
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$(foreach src_file, $(src), $(moore) compile $(src_file);)
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# User Verilator to lint the target
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lint:
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verilator ${src} --lint-only \
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@ -79,4 +84,4 @@ clean:
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rm -rf work/ *.ucdb
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.PHONY:
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build lint
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build lint build-moore
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@ -16,6 +16,7 @@ package ariane_pkg;
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localparam TRANS_ID_BITS = $clog2(NR_SB_ENTRIES); // depending on the number of scoreboard entries we need that many bits
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// to uniquely identify the entry in the scoreboard
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localparam NR_WB_PORTS = 3;
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localparam ASID_WIDTH = 1;
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localparam ISA_CODE = (1 << 2) // C - Compressed extension
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| (1 << 8) // I - RV32I/64I/128I base ISA
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| (1 << 12) // M - Integer Multiply/Divide extension
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@ -126,7 +126,6 @@ module ariane
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logic [TRANS_ID_BITS-1:0] csr_trans_id_ex_id;
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logic [63:0] csr_result_ex_id;
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logic csr_valid_ex_id;
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// --------------
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// EX <-> COMMIT
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// --------------
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@ -163,7 +162,19 @@ module ariane
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logic [0:0] asid_csr_ex;
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logic flush_tlb_csr_ex;
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logic [11:0] csr_addr_ex_csr;
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// --------------
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// COMMIT <-> CSR
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// --------------
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exception ex_commit_csr;
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fu_op csr_op_commit_csr;
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logic [63:0] csr_wdata_commit_csr;
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logic [63:0] csr_rdata_csr_commit;
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logic [63:0] pc_commit_csr;
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logic [3:0] irq_enable_csr_commit;
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exception csr_exception_csr_commit;
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// --------------
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// EX <-> CSR
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// --------------
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// TODO: Preliminary signal assignments
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logic flush_tlb;
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@ -172,7 +183,13 @@ module ariane
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assign id_ready_i = 1'b1;
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assign halt_if = 1'b0;
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// --------------
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// NPC Generation
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// --------------
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// ---------
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// IF
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// ---------
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if_stage if_stage_i (
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.flush_i ( flush ),
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.req_i ( fetch_enable ),
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@ -195,7 +212,9 @@ module ariane
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.boot_addr_i ( boot_addr_i ), // TODO
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.*
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);
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// ---------
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// ID
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// ---------
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id_stage
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#(
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.NR_ENTRIES ( NR_SB_ENTRIES ),
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@ -226,13 +245,13 @@ module ariane
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.mult_ready_i ( ),
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.mult_valid_o ( ),
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.csr_ready_i ( ),
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.csr_valid_o ( ),
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.csr_ready_i ( csr_ready_ex_id ),
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.csr_valid_o ( csr_valid_id_ex ),
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.trans_id_i ( {alu_trans_id_ex_id, lsu_trans_id_ex_id} ),
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.wdata_i ( {alu_result_ex_id, lsu_result_ex_id} ),
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.ex_ex_i ( {'b0, lsu_exception_ex_id } ),
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.wb_valid_i ( {alu_valid_ex_id, lsu_valid_ex_id} ),
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.trans_id_i ( {alu_trans_id_ex_id, lsu_trans_id_ex_id , csr_trans_id_ex_id} ),
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.wdata_i ( {alu_result_ex_id, lsu_result_ex_id, csr_result_ex_id} ),
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.ex_ex_i ( {'b0, lsu_exception_ex_id, 'b0 } ),
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.wb_valid_i ( {alu_valid_ex_id, lsu_valid_ex_id, csr_valid_ex_id} ),
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.waddr_a_i ( waddr_a_commit_id ),
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.wdata_a_i ( wdata_a_commit_id ),
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@ -242,15 +261,9 @@ module ariane
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.commit_ack_i ( commit_ack_commit_id ),
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.*
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);
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// ---------
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// EX
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// ---------
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ex_stage ex_stage_i (
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.flush_i ( flush ),
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.operator_i ( operator_id_ex ),
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@ -282,7 +295,7 @@ module ariane
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.csr_addr_o ( csr_addr_ex_csr ),
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.csr_commit_i ( csr_commit_commit_ex ), // from commit
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// memory management
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.enable_translation_i ( 1'b0 ), // from CSR
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.enable_translation_i ( enable_translation_csr_ex ), // from CSR
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.fetch_req_i ( fetch_req_if_ex ),
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.fetch_gnt_o ( fetch_gnt_ex_if ),
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.fetch_valid_o ( fetch_valid_ex_if ),
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@ -300,17 +313,57 @@ module ariane
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.mult_valid_i ( mult_valid_id_ex ),
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.*
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);
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// ---------
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// Commit
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// ---------
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commit_stage commit_stage_i (
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.priv_lvl_o ( priv_lvl ),
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.exception_o ( ),
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.exception_o ( ex_commit_csr ),
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.commit_instr_i ( commit_instr_id_commit ),
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.commit_ack_o ( commit_ack_commit_id ),
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.waddr_a_o ( waddr_a_commit_id ),
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.wdata_a_o ( wdata_a_commit_id ),
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.we_a_o ( we_a_commit_id ),
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.commit_lsu_o ( lsu_commit_commit_ex ),
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.commit_csr_o ( csr_commit_commit_ex ),
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.pc_o ( pc_commit_csr ),
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.csr_op_o ( csr_op_commit_csr ),
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.csr_wdata_o ( csr_wdata_commit_csr ),
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.csr_rdata_i ( csr_rdata_csr_commit ),
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.csr_exception_i ( csr_exception_csr_commit ),
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.irq_enable_i ( irq_enable_csr_commit ),
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.*
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);
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// ---------
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// CSR
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// ---------
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csr_regfile #(
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.ASID_WIDTH ( ASID_WIDTH )
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)
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csr_regfile_i (
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.ex_i ( ex_commit_csr ),
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.csr_op_i ( csr_op_commit_csr ),
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.csr_addr_i ( csr_addr_ex_csr ),
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.csr_wdata_i ( csr_wdata_commit_csr ),
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.csr_rdata_o ( csr_rdata_csr_commit ),
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.pc_i ( pc_commit_csr ),
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.csr_exception_o ( csr_exception_o ),
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.irq_enable_o ( irq_enable_o ),
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.epc_o ( ),
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.trap_vector_base_o ( ),
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.priv_lvl_o ( priv_lvl ),
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.enable_translation_o ( enable_translation_csr_ex ),
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.flag_pum_o ( flag_pum_csr_ex ),
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.flag_mxr_o ( flag_mxr_csr_ex ),
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.pd_ppn_o ( pd_ppn_csr_ex ),
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.asid_o ( asid_csr_ex ),
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.*
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);
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// ------------
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// Controller
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// ------------
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if(~rst_ni) begin
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@ -32,13 +32,24 @@ module commit_stage (
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// to register file
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output logic[4:0] waddr_a_o,
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output logic[63:0] wdata_a_o,
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output logic we_a_o
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output logic we_a_o,
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// to/from CSR file
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output logic [63:0] pc_o,
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input fu_op csr_op_o,
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output logic [63:0] csr_wdata_o,
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output logic [63:0] csr_rdata_i,
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input exception csr_exception_i,
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// to ex
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output logic commit_lsu_o,
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output logic commit_csr_o,
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// general control signal
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input logic [4:0] irq_enable_i
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);
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assign waddr_a_o = commit_instr_i.rd;
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assign wdata_a_o = commit_instr_i.result;
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assign pc_o = commit_instr_i.pc;
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// commit instruction
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// write register file
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always_comb begin : commit
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@ -32,7 +32,7 @@ module csr_regfile #(
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// we are taking an exception
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input exception ex_i,
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input fu_op [1:0] csr_op_i,
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input fu_op csr_op_i,
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input logic [11:0] csr_addr_i,
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input logic [63:0] csr_wdata_i,
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output logic [63:0] csr_rdata_o,
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@ -45,9 +45,6 @@ module csr_regfile #(
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output logic [31:0] epc_o,
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output logic [31:0] trap_vector_base_o,
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output priv_lvl_t priv_lvl_o,
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input logic [63:0] badaddr_i,
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input logic [63:0] exc_cause_i,
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input logic save_exc_cause_i,
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// MMU
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output logic enable_translation_o,
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output logic flag_pum_o,
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@ -205,10 +202,10 @@ module csr_regfile #(
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mstatus_n = csr_wdata;
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// hardwired zero registers
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mstatus_n.sd = 1'b0;
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mstatus.xs = 2'b0;
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mstatus.fs = 2'b0;
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mstatus.upie = 1'b0;
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mstatus.uie = 1'b0;
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mstatus_n.xs = 2'b0;
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mstatus_n.fs = 2'b0;
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mstatus_n.upie = 1'b0;
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mstatus_n.uie = 1'b0;
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end
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// machine exception delegation register
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// 0 - 12 exceptions supported
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@ -121,7 +121,7 @@ module ex_stage #(
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// -----
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// CSR
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// -----
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// CSR address buffer
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csr_buffer csr_buffer_i (
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.commit_i ( csr_commit_i ),
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.*
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