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🐛 Fixes in memory arbiter
This commit is contained in:
Florian Zaruba
parent
85d2ca6821
commit
b105b262ba
3 changed files with 35 additions and 71 deletions
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@ -51,7 +51,7 @@ module mem_arbiter #(
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input logic [NR_PORTS-1:0] data_req_i,
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input logic [NR_PORTS-1:0] data_we_i,
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input logic [NR_PORTS-1:0][7:0] data_be_i,
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input logic [1:0] data_tag_status_i,
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input logic [NR_PORTS-1:0][1:0] data_tag_status_i,
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output logic [NR_PORTS-1:0] data_gnt_o,
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output logic [NR_PORTS-1:0] data_rvalid_o,
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output logic [NR_PORTS-1:0][63:0] data_rdata_o
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@ -98,19 +98,13 @@ module mem_arbiter #(
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// addressing read and full write
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always_comb begin : read_req_write
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automatic logic [DATA_WIDTH-1:0] request_index;
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// pass through all signals from the correct slave port
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address_o = address_i[request_index];
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automatic logic [DATA_WIDTH-1:0] request_index = 0;
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data_req_o = 1'b0;
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data_wdata_o = data_wdata_i[request_index];
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data_be_o = data_be_i[request_index];
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data_we_o = data_we_i[request_index];
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data_tag_status_o = data_tag_status_i[request_index];
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data_gnt_o[request_index] = data_gnt_i;
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in_data = '{default: 0};
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push = 1'b0;
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request_port_n = request_port_q;
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NS = CS;
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for (int i = 0; i < NR_PORTS; i++)
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data_gnt_o[i] = 1'b0;
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@ -216,6 +210,14 @@ module mem_arbiter #(
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end
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default : /* default */;
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endcase
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// pass through all signals from the correct slave port
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address_o = address_i[request_index];
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data_wdata_o = data_wdata_i[request_index];
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data_be_o = data_be_i[request_index];
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data_we_o = data_we_i[request_index];
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data_tag_status_o = data_tag_status_i[request_index];
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data_gnt_o[request_index] = data_gnt_i;
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// if we got a flush and we are not ready for the flush wait and for it and don't accept any incoming data
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// e.g.: jump to the flush wait state
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if (flush_i && !flush_ready)
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@ -38,27 +38,29 @@ module mem_arbiter_tb;
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// assign data_gnt = data_gnt_driver & data_req;
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mem_arbiter dut (
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.clk_i ( clk ),
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.rst_ni ( rst_ni ),
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.flush_ready_o ( flush_ready_o ),
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.clk_i ( clk ),
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.rst_ni ( rst_ni ),
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.flush_i ( 1'b0 ),
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.address_o ( slave.address ),
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.data_wdata_o ( slave.data_wdata ),
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.data_req_o ( slave.data_req ),
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.data_we_o ( slave.data_we ),
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.data_be_o ( slave.data_be ),
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.data_gnt_i ( slave.data_req & slave.data_gnt ),
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.data_rvalid_i ( slave.data_rvalid ),
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.data_rdata_i ( slave.data_rdata ),
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.address_o ( slave.address ),
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.data_wdata_o ( slave.data_wdata ),
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.data_req_o ( slave.data_req ),
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.data_we_o ( slave.data_we ),
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.data_be_o ( slave.data_be ),
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.data_tag_status_o ( ),
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.data_gnt_i ( slave.data_req & slave.data_gnt ),
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.data_rvalid_i ( slave.data_rvalid ),
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.data_rdata_i ( slave.data_rdata ),
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.address_i ( {master[2].address, master[1].address, master[0].address} ),
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.data_wdata_i ( {master[2].data_wdata, master[1].data_wdata, master[0].data_wdata} ),
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.data_req_i ( {master[2].data_req, master[1].data_req, master[0].data_req} ),
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.data_we_i ( {master[2].data_we, master[1].data_we, master[0].data_we} ),
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.data_be_i ( {master[2].data_be, master[1].data_be, master[0].data_be} ),
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.data_gnt_o ( {master[2].data_gnt, master[1].data_gnt, master[0].data_gnt} ),
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.data_rvalid_o ( {master[2].data_rvalid, master[1].data_rvalid, master[0].data_rvalid} ),
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.data_rdata_o ( {master[2].data_rdata, master[1].data_rdata, master[0].data_rdata} )
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.address_i ( {master[2].address, master[1].address, master[0].address} ),
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.data_wdata_i ( {master[2].data_wdata, master[1].data_wdata, master[0].data_wdata} ),
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.data_req_i ( {master[2].data_req, master[1].data_req, master[0].data_req} ),
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.data_we_i ( {master[2].data_we, master[1].data_we, master[0].data_we} ),
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.data_be_i ( {master[2].data_be, master[1].data_be, master[0].data_be} ),
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.data_tag_status_i ( {2'b01, 2'b01, 2'b01 } ),
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.data_gnt_o ( {master[2].data_gnt, master[1].data_gnt, master[0].data_gnt} ),
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.data_rvalid_o ( {master[2].data_rvalid, master[1].data_rvalid, master[0].data_rvalid} ),
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.data_rdata_o ( {master[2].data_rdata, master[1].data_rdata, master[0].data_rdata} )
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);
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initial begin
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@ -1,48 +1,8 @@
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate /mem_arbiter_tb/dut/clk_i
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add wave -noupdate /mem_arbiter_tb/dut/rst_ni
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add wave -noupdate /mem_arbiter_tb/dut/flush_ready_o
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add wave -noupdate -expand -group Slave /mem_arbiter_tb/dut/address_o
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add wave -noupdate -expand -group Slave /mem_arbiter_tb/dut/data_wdata_o
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add wave -noupdate -expand -group Slave /mem_arbiter_tb/dut/data_req_o
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add wave -noupdate -expand -group Slave /mem_arbiter_tb/dut/data_we_o
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add wave -noupdate -expand -group Slave /mem_arbiter_tb/dut/data_be_o
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add wave -noupdate -expand -group Slave /mem_arbiter_tb/dut/data_gnt_i
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add wave -noupdate -expand -group Slave /mem_arbiter_tb/dut/data_rvalid_i
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add wave -noupdate -expand -group Slave /mem_arbiter_tb/dut/data_rdata_i
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add wave -noupdate -expand -group Master /mem_arbiter_tb/dut/address_i
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add wave -noupdate -expand -group Master /mem_arbiter_tb/dut/data_wdata_i
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add wave -noupdate -expand -group Master -expand /mem_arbiter_tb/dut/data_req_i
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add wave -noupdate -expand -group Master /mem_arbiter_tb/dut/data_we_i
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add wave -noupdate -expand -group Master /mem_arbiter_tb/dut/data_be_i
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add wave -noupdate -expand -group Master -expand /mem_arbiter_tb/dut/data_gnt_o
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add wave -noupdate -expand -group Master -expand /mem_arbiter_tb/dut/data_rvalid_o
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add wave -noupdate -expand -group Master -expand /mem_arbiter_tb/dut/data_rdata_o
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add wave -noupdate /mem_arbiter_tb/dut/full_o
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add wave -noupdate /mem_arbiter_tb/dut/empty_o
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add wave -noupdate /mem_arbiter_tb/dut/data_i
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add wave -noupdate /mem_arbiter_tb/dut/push_i
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add wave -noupdate /mem_arbiter_tb/dut/data_o
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add wave -noupdate /mem_arbiter_tb/dut/pop_i
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add wave -noupdate -expand -group FIFO /mem_arbiter_tb/dut/fifo_i/clk_i
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add wave -noupdate -expand -group FIFO /mem_arbiter_tb/dut/fifo_i/rst_ni
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add wave -noupdate -expand -group FIFO /mem_arbiter_tb/dut/fifo_i/flush_i
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add wave -noupdate -expand -group FIFO /mem_arbiter_tb/dut/fifo_i/full_o
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add wave -noupdate -expand -group FIFO /mem_arbiter_tb/dut/fifo_i/empty_o
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add wave -noupdate -expand -group FIFO /mem_arbiter_tb/dut/fifo_i/single_element_o
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add wave -noupdate -expand -group FIFO /mem_arbiter_tb/dut/fifo_i/data_i
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add wave -noupdate -expand -group FIFO /mem_arbiter_tb/dut/fifo_i/push_i
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add wave -noupdate -expand -group FIFO /mem_arbiter_tb/dut/fifo_i/data_o
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add wave -noupdate -expand -group FIFO /mem_arbiter_tb/dut/fifo_i/pop_i
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add wave -noupdate -expand -group FIFO /mem_arbiter_tb/dut/fifo_i/read_pointer_n
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add wave -noupdate -expand -group FIFO /mem_arbiter_tb/dut/fifo_i/read_pointer_q
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add wave -noupdate -expand -group FIFO /mem_arbiter_tb/dut/fifo_i/write_pointer_n
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add wave -noupdate -expand -group FIFO /mem_arbiter_tb/dut/fifo_i/write_pointer_q
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add wave -noupdate -expand -group FIFO /mem_arbiter_tb/dut/fifo_i/status_cnt_n
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add wave -noupdate -expand -group FIFO /mem_arbiter_tb/dut/fifo_i/status_cnt_q
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add wave -noupdate -expand -group FIFO /mem_arbiter_tb/dut/fifo_i/mem_n
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add wave -noupdate -expand -group FIFO /mem_arbiter_tb/dut/fifo_i/mem_q
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add wave -noupdate /mem_arbiter_tb/dut/*
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add wave -noupdate -group FIFO /mem_arbiter_tb/dut/fifo_i/*
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 1} {421 ns} 0}
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quietly wave cursor active 1
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