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dtlb_lu_access is done only when misalgined ex valid is 0 (#2989)
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This fixes issue #2988 and #2827

---------

Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
This commit is contained in:
khandelwaltanuj 2025-06-17 08:00:48 +02:00 • committed by GitHub
parent f3d2ec4461
commit b484f5f3ee
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2 changed files with 6 additions and 2 deletions
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6
config/gen_from_riscv_config/scripts/libs/utils.py
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@ -1273,7 +1273,11 @@ class CsrParser:
if isinstance(RegElement.get("address", None), str)
else hex(RegElement.get("address", None))
)
reset = hex(RegElement.get("reset-val", ""))
if RegElement.get("reset-val", "") != "":
reset = hex(RegElement.get("reset-val", ""))
else:
print(regName, "reset val not defined")
access = RegElement.get("priv_mode", "")
if Registers.get(register, {}).get("description", "") is not None:

2
core/cva6_mmu/cva6_mmu.sv
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@ -170,7 +170,7 @@ module cva6_mmu
// Assignments
assign itlb_lu_access = icache_areq_i.fetch_req;
assign dtlb_lu_access = lsu_req_i;
assign dtlb_lu_access = lsu_req_i & !misaligned_ex_i.valid;
assign itlb_lu_asid = v_i ? vs_asid_i : asid_i;
assign dtlb_lu_asid = (ld_st_v_i || flush_tlb_vvma_i) ? vs_asid_i : asid_i;