mirror of
https://github.com/openhwgroup/cva6.git
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Use unique CVA6 Flist for testharness, UVM and FPGA (#1005)
This commit is contained in:
JeanRochCoulon
GitHub
parent
d209b0406d
commit
b5b3abd7d9
1 changed files with 19 additions and 57 deletions
76
Makefile
76
Makefile
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@ -42,6 +42,11 @@ BOARD ?= genesys2
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mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST)))
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root-dir := $(dir $(mkfile_path))
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ifndef CVA6_REPO_DIR
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$(warning must set CVA6_REPO_DIR to point at the root of CVA6 sources -- doing it for you...)
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export CVA6_REPO_DIR = $(abspath $(root-dir))
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endif
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support_verilator_4 := $(shell ($(verilator) --version | grep '4\.') > /dev/null 2>&1 ; echo $$?)
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ifeq ($(support_verilator_4), 0)
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verilator_threads := 1
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@ -85,25 +90,11 @@ target ?= cv64a6_imafdc_sv39
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# Sources
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# Package files -> compile first
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ariane_pkg := core/include/$(target)_config_pkg.sv
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ariane_pkg += core/include/riscv_pkg.sv \
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corev_apu/riscv-dbg/src/dm_pkg.sv \
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core/include/ariane_pkg.sv \
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core/include/ariane_rvfi_pkg.sv \
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core/include/wt_cache_pkg.sv \
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core/include/cvxif_pkg.sv \
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corev_apu/axi/src/axi_pkg.sv \
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ariane_pkg := \
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corev_apu/register_interface/src/reg_intf.sv \
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core/include/axi_intf.sv \
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corev_apu/tb/rvfi_pkg.sv \
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corev_apu/tb/ariane_soc_pkg.sv \
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corev_apu/tb/ariane_axi_soc_pkg.sv \
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core/include/ariane_axi_pkg.sv \
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core/include/std_cache_pkg.sv \
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core/fpu/src/fpnew_pkg.sv \
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common/submodules/common_cells/src/cf_math_pkg.sv \
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core/cvxif_example/include/cvxif_instr_pkg.sv \
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core/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
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corev_apu/tb/ariane_axi_soc_pkg.sv
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ariane_pkg := $(addprefix $(root-dir), $(ariane_pkg))
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# utility modules
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@ -156,13 +147,7 @@ endif
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# this list contains the standalone components
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src := $(filter-out core/ariane_regfile.sv, $(wildcard core/*.sv)) \
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$(filter-out core/fpu/src/fpnew_pkg.sv, $(wildcard core/fpu/src/*.sv)) \
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$(filter-out core/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv, \
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$(wildcard core/fpu/src/fpu_div_sqrt_mvp/hdl/*.sv)) \
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$(wildcard core/frontend/*.sv) \
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$(filter-out core/cache_subsystem/std_no_dcache.sv, \
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$(wildcard core/cache_subsystem/*.sv)) \
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src := core/axi_adapter.sv \
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$(wildcard corev_apu/bootrom/*.sv) \
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$(wildcard corev_apu/clint/*.sv) \
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$(wildcard corev_apu/fpga/src/axi2apb/src/*.sv) \
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@ -170,8 +155,6 @@ src := $(filter-out core/ariane_regfile.sv, $(wildcard core/*.sv))
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$(wildcard corev_apu/fpga/src/axi_slice/src/*.sv) \
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$(wildcard corev_apu/src/axi_riscv_atomics/src/*.sv) \
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$(wildcard corev_apu/axi_mem_if/src/*.sv) \
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$(wildcard core/pmp/src/*.sv) \
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$(wildcard core/cvxif_example/*.sv) \
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corev_apu/rv_plic/rtl/rv_plic_target.sv \
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corev_apu/rv_plic/rtl/rv_plic_gateway.sv \
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corev_apu/rv_plic/rtl/plic_regmap.sv \
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@ -203,34 +186,17 @@ src := $(filter-out core/ariane_regfile.sv, $(wildcard core/*.sv))
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corev_apu/axi/src/axi_mux.sv \
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corev_apu/axi/src/axi_demux.sv \
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corev_apu/axi/src/axi_xbar.sv \
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common/local/techlib/fpga/rtl/SyncSpRamBeNx64.sv \
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common/submodules/common_cells/src/unread.sv \
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common/submodules/common_cells/src/sync.sv \
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common/submodules/common_cells/src/cdc_2phase.sv \
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common/submodules/common_cells/src/spill_register_flushable.sv \
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common/submodules/common_cells/src/spill_register.sv \
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common/submodules/common_cells/src/sync_wedge.sv \
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common/submodules/common_cells/src/edge_detect.sv \
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common/submodules/common_cells/src/stream_arbiter.sv \
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common/submodules/common_cells/src/stream_arbiter_flushable.sv \
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common/submodules/common_cells/src/deprecated/fifo_v1.sv \
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common/submodules/common_cells/src/deprecated/fifo_v2.sv \
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common/submodules/common_cells/src/fifo_v3.sv \
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common/submodules/common_cells/src/lzc.sv \
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common/submodules/common_cells/src/popcount.sv \
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common/submodules/common_cells/src/rr_arb_tree.sv \
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common/submodules/common_cells/src/deprecated/rrarbiter.sv \
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common/submodules/common_cells/src/stream_delay.sv \
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common/submodules/common_cells/src/lfsr.sv \
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common/submodules/common_cells/src/lfsr_8bit.sv \
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common/submodules/common_cells/src/lfsr_16bit.sv \
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common/submodules/common_cells/src/delta_counter.sv \
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common/submodules/common_cells/src/counter.sv \
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common/submodules/common_cells/src/shift_reg.sv \
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corev_apu/src/tech_cells_generic/src/deprecated/cluster_clk_cells.sv \
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corev_apu/src/tech_cells_generic/src/deprecated/pulp_clk_cells.sv \
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common/local/util/tc_sram_wrapper.sv \
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corev_apu/src/tech_cells_generic/src/rtl/tc_sram.sv \
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corev_apu/src/tech_cells_generic/src/rtl/tc_clk.sv \
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corev_apu/tb/ariane_testharness.sv \
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corev_apu/tb/ariane_peripherals.sv \
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@ -255,7 +221,7 @@ copro_src := $(addprefix $(root-dir), $(copro_src))
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uart_src := $(wildcard corev_apu/fpga/src/apb_uart/src/*.vhd)
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uart_src := $(addprefix $(root-dir), $(uart_src))
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fpga_src := $(wildcard corev_apu/fpga/src/*.sv) $(wildcard corev_apu/fpga/src/bootrom/*.sv) $(wildcard corev_apu/fpga/src/ariane-ethernet/*.sv) common/local/util/tc_sram_fpga_wrapper.sv
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fpga_src := $(wildcard corev_apu/fpga/src/*.sv) $(wildcard corev_apu/fpga/src/bootrom/*.sv) $(wildcard corev_apu/fpga/src/ariane-ethernet/*.sv) common/local/util/tc_sram_fpga_wrapper.sv common/local/techlib/fpga/rtl/SyncSpRamBeNx64.sv
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fpga_src := $(addprefix $(root-dir), $(fpga_src))
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# look for testbenches
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@ -324,12 +290,11 @@ endif
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vcs_build: $(dpi-library)/ariane_dpi.so
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mkdir -p $(vcs-library)
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cd $(vcs-library) &&\
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vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -ntb_opts uvm-1.2 &&\
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vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -ntb_opts uvm-1.2 +define+$(defines) $(filter %.sv,$(ariane_pkg)) +incdir+core/include/+$(VCS_HOME)/etc/uvm-1.2/dpi &&\
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vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -ntb_opts uvm-1.2 +define+$(defines) $(filter %.sv,$(util)) +incdir+../common/local/util+../core/include/+src/util/+$(VCS_HOME)/etc/uvm-1.2/dpi &&\
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vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog +define+$(defines) -f ../core/Flist.$(target) &&\
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vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog +define+$(defines) $(filter %.sv,$(ariane_pkg)) +incdir+core/include/+$(VCS_HOME)/etc/uvm-1.2/dpi &&\
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vhdlan $(if $(VERDI), -kdb,) -full64 -nc $(filter %.vhd,$(uart_src)) &&\
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vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -ntb_opts uvm-1.2 $(filter %.sv,$(copro_src)) &&\
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vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -ntb_opts uvm-1.2 -assert svaext +define+$(defines) $(filter %.sv,$(src)) +incdir+../core/include/+../common/submodules/common_cells/include/+../common/local/util/+../corev_apu/axi/include/+../corev_apu/register_interface/include/+$(VCS_HOME)/etc/uvm-1.2/dpi &&\
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vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -assert svaext +define+$(defines) $(filter %.sv,$(src)) +incdir+../common/submodules/common_cells/include/+../corev_apu/axi/include/+../corev_apu/register_interface/include/ &&\
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vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -ntb_opts uvm-1.2 &&\
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vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -ntb_opts uvm-1.2 $(tbs) +define+$(defines) +incdir+../corev_apu/axi/include/ &&\
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vcs $(if $(VERDI), -kdb -debug_access+all -lca,) -full64 -timescale=1ns/1ns -ntb_opts uvm-1.2 work.ariane_tb
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@ -344,12 +309,10 @@ build: $(library) $(library)/.build-srcs $(library)/.build-tb $(dpi-library)/ari
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# src files
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$(library)/.build-srcs: $(util) $(library)
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$(VLOG) $(compile_flag) -work $(library) $(filter %.sv,$(ariane_pkg)) $(list_incdir) -suppress 2583
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# $(VCOM) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(ariane_pkg))
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$(VLOG) $(compile_flag) -timescale "1ns / 1ns" -work $(library) $(filter %.sv,$(util)) $(list_incdir) -suppress 2583
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# Suppress message that always_latch may not be checked thoroughly by QuestaSim.
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$(VCOM) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(uart_src))
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# $(VCOM) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(src))
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$(VLOG) $(compile_flag) -timescale "1ns / 1ns" -work $(library) -pedanticerrors $(filter %.sv,$(src)) $(list_incdir) -suppress 2583
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$(VLOG) $(compile_flag) -timescale "1ns / 1ns" -work $(library) -pedanticerrors -f ../core/Flist.$(target) $(list_incdir) -suppress 2583
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touch $(library)/.build-srcs
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# build TBs
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@ -478,9 +441,9 @@ XRUN_COMP = $(XRUN_COMP_FLAGS) \
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$(XRUN_DISABLED_WARNINGS) \
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$(XRUN_INCDIR) \
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$(filter %.sv, $(ariane_pkg)) \
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$(filter %.sv, $(util)) \
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$(filter %.vhd, $(uart_src)) \
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$(filter %.sv, $(src)) \
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-f ../core/Flist.$(target) \
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$(filter %.sv, $(XRUN_TB)) \
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XRUN_RUN = $(XRUN_RUN_FLAGS) \
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@ -584,11 +547,10 @@ xrun-ci: xrun-asm-tests xrun-amo-tests xrun-mul-tests xrun-fp-tests xrun-benchma
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# verilator-specific
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verilate_command := $(verilator) \
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-f core/Flist.$(target) \
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$(filter-out %.vhd, $(ariane_pkg)) \
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$(filter-out core/fpu_wrap.sv, $(filter-out %.vhd, $(src))) \
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$(copro_src) \
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+define+$(defines)$(if $(TRACE_FAST),+VM_TRACE)$(if $(TRACE_COMPACT),+VM_TRACE+VM_TRACE_FST) \
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common/local/util/sram.sv \
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corev_apu/tb/common/mock_uart.sv \
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+incdir+corev_apu/axi_node \
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$(if $(verilator_threads), --threads $(verilator_threads)) \
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@ -764,6 +726,7 @@ check-torture:
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grep 'All signatures match for $(test-location)' $(riscv-torture-dir)/$(test-location).log
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diff -s $(riscv-torture-dir)/$(test-location).spike.sig $(riscv-torture-dir)/$(test-location).rtlsim.sig
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src_flist := $(addprefix $(root-dir), $(shell cat core/Flist.$(target)|grep "$\{CVA6_REPO_DIR.\+sv"|sed "s/.*CVA6_REPO_DIR..//"))
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fpga_filter := $(addprefix $(root-dir), corev_apu/bootrom/bootrom.sv)
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fpga_filter += $(addprefix $(root-dir), core/include/instr_tracer_pkg.sv)
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fpga_filter += $(addprefix $(root-dir), src/util/ex_trace_item.sv)
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@ -773,12 +736,11 @@ fpga_filter += $(addprefix $(root-dir), common/local/util/instr_tracer.sv)
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fpga_filter += $(addprefix $(root-dir), corev_apu/src/tech_cells_generic/src/rtl/tc_sram.sv)
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fpga_filter += $(addprefix $(root-dir), common/local/util/tc_sram_wrapper.sv)
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fpga: $(ariane_pkg) $(util) $(src) $(fpga_src) $(uart_src) $(copro_src)
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fpga: $(ariane_pkg) $(src) $(fpga_src) $(uart_src) $(src_flist)
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@echo "[FPGA] Generate sources"
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@echo read_vhdl {$(uart_src)} > corev_apu/fpga/scripts/add_sources.tcl
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@echo read_verilog -sv {$(ariane_pkg)} >> corev_apu/fpga/scripts/add_sources.tcl
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@echo read_verilog -sv {$(filter-out $(fpga_filter), $(util))} >> corev_apu/fpga/scripts/add_sources.tcl
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@echo read_verilog -sv {$(filter-out $(fpga_filter), $(copro_src))} >> corev_apu/fpga/scripts/add_sources.tcl
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@echo read_verilog -sv {$(filter-out $(fpga_filter), $(src_flist))} >> corev_apu/fpga/scripts/add_sources.tcl
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@echo read_verilog -sv {$(filter-out $(fpga_filter), $(src))} >> corev_apu/fpga/scripts/add_sources.tcl
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@echo read_verilog -sv {$(fpga_src)} >> corev_apu/fpga/scripts/add_sources.tcl
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@echo "[FPGA] Generate Bitstream"
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