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🐛 Fix missing pin, wrong fetch data width

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This commit is contained in:
Florian Zaruba 2017-05-03 18:29:36 +02:00
parent 1022c50511
commit b5e62fd91b
7 changed files with 51 additions and 20 deletions
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37
docs/block_details.md
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@ -311,3 +311,40 @@ The memory arbiter's purpose is to arbitrate the memory accesses coming/going fr
The store queue keeps track of all stores. It has two entries: One is for already committed instructions and one is for outstanding instructions. On a flush only the instruction which has the already committed instruction saved persists its data. But on a flush it can't request further to the memory since this could potentially stall us indefinitely because of the property of the memory arbiter (see above).
The store queue works with physical addresses only. At the time when they are committed the translation is correct. Furthermore the store queue directly outputs the address and value of the instruction it is going to commit since any subsequent store also needs to check for the address.
# Cache
## Interface
```verilog
input logic clk,
input logic rst_n,
// Data Port (TLB or CORE )
input logic [DATA_WIDTH-1:0] data_wdata_i,
input logic data_req_i,
input logic [BE_WIDTH-1:0] data_be_i,
input logic data_we_i,
input logic [ADDR_WIDTH-1:0] data_add_i,
input logic [ID_WIDTH-1:0] data_ID_i,
output logic data_gnt_o,
output logic [DATA_WIDTH-1:0] data_r_rdata_o,
output logic data_r_valid_o,
input logic [ID_WIDTH-1:0] data_r_ID_o,
input logic data_r_gnt_i,
//Service Port (32bit)
input logic conf_req_i,
input logic [31:0] conf_addr_i,
input logic conf_wen_i,
input logic [31:0] conf_wdata_i,
input logic [3:0] conf_be_i,
input logic [PE_ID_WIDTH-1:0] conf_id_i,
output logic conf_gnt_o,
output logic conf_r_valid_o,
output logic conf_r_opc_o,
output logic [PE_ID_WIDTH-1:0] conf_r_id_o,
output logic [31:0] conf_r_rdata_o,
```

2
src/ariane.sv
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@ -33,7 +33,7 @@ module ariane
output logic [7:0] instr_if_data_be_o,
input logic instr_if_data_gnt_i,
input logic instr_if_data_rvalid_i,
input logic [63:0] instr_if_data_rdata_i,
input logic [31:0] instr_if_data_rdata_i,
// Data memory interface
output logic [63:0] data_if_address_o,
output logic [63:0] data_if_data_wdata_o,

2
src/ex_stage.sv
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@ -66,7 +66,7 @@ module ex_stage #(
output logic [7:0] instr_if_data_be_o,
input logic instr_if_data_gnt_i,
input logic instr_if_data_rvalid_i,
input logic [63:0] instr_if_data_rdata_i,
input logic [31:0] instr_if_data_rdata_i,
output logic [63:0] data_if_address_o,
output logic [63:0] data_if_data_wdata_o,

8
src/lsu.sv
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@ -58,7 +58,7 @@ module lsu #(
output logic [7:0] instr_if_data_be_o,
input logic instr_if_data_gnt_i,
input logic instr_if_data_rvalid_i,
input logic [63:0] instr_if_data_rdata_i,
input logic [31:0] instr_if_data_rdata_i,
// Data memory/cache
output logic [63:0] data_if_address_o,
output logic [63:0] data_if_data_wdata_o,
@ -77,7 +77,7 @@ module lsu #(
// data is misaligned
logic data_misaligned;
enum logic [3:0] { IDLE, STORE, LOAD_WAIT_TRANSLATION, LOAD_WAIT_GNT, LOAD_WAIT_RVALID } CS, NS;
enum logic [2:0] { IDLE, STORE, LOAD_WAIT_TRANSLATION, LOAD_WAIT_GNT, LOAD_WAIT_RVALID } CS, NS;
// virtual address as calculated by the AGU in the first cycle
logic [63:0] vaddr_i;
@ -167,8 +167,8 @@ module lsu #(
// MMU e.g.: TLBs/PTW
// -------------------
mmu #(
.INSTR_TLB_ENTRIES ( 16 ),
.DATA_TLB_ENTRIES ( 16 ),
.INSTR_TLB_ENTRIES ( 4 ),
.DATA_TLB_ENTRIES ( 4 ),
.ASID_WIDTH ( ASID_WIDTH )
) i_mmu (
.lsu_req_i ( translation_req ),

4
src/mmu.sv
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@ -60,7 +60,7 @@ module mmu #(
output logic [7:0] instr_if_data_be_o,
input logic instr_if_data_gnt_i,
input logic instr_if_data_rvalid_i,
input logic [63:0] instr_if_data_rdata_i,
input logic [31:0] instr_if_data_rdata_i,
// Data memory/cache
output logic [63:0] data_if_address_o,
output logic [63:0] data_if_data_wdata_o,
@ -273,7 +273,7 @@ module mmu #(
// lsu_vaddr_i
// lsu_valid_o
// lsu_paddr_o
lsu_paddr_o = (enable_translation_i) ? dtlb_content : lsu_vaddr_i;
lsu_paddr_o = (enable_translation_i) ? {16'b0, dtlb_content} : lsu_vaddr_i;
lsu_valid_o = lsu_req_i;
end

6
src/ptw.sv
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@ -70,7 +70,7 @@ module ptw #(
pte_t ptw_pte_i;
assign ptw_pte_i = pte_t'(data_rdata_i);
enum logic[3:0] {
enum logic[1:0] {
PTW_READY,
PTW_WAIT_GRANT,
PTW_PTE_LOOKUP,
@ -152,7 +152,7 @@ module ptw #(
// if we got an ITLB miss
if (enable_translation_i & itlb_access_i & itlb_miss_i & ~dtlb_access_i) begin
ptw_pptr_n = {pd_ppn_i, itlb_vaddr_i[38:30]};
is_instr_ptw_n = 1'b0;
is_instr_ptw_n = 1'b1;
tlb_update_asid_n = asid_i;
tlb_update_vpn_n = itlb_vaddr_i[38:12];
ptw_state_n = PTW_WAIT_GRANT;
@ -241,8 +241,6 @@ module ptw #(
ptw_error_o = 1'b1;
end
default:
ptw_state_n = PTW_READY;
endcase // ptw_state_q
end

12
tb/lsu_tb.sv
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@ -47,7 +47,7 @@ module lsu_tb;
.lsu_valid_o ( lsu.result_valid ),
.commit_i ( lsu.commit ),
// we are currently no testing the PTW and MMU
.enable_translation_i ( 1'b1 ),
.enable_translation_i ( 1'b0 ),
.fetch_req_i ( 1'b0 ),
.fetch_gnt_o ( ),
.fetch_valid_o ( ),
@ -64,7 +64,7 @@ module lsu_tb;
.instr_if_address_o ( instr_if.address ),
.instr_if_data_req_o ( instr_if.data_req ),
.instr_if_data_be_o ( instr_if.data_be ),
.instr_if_data_gnt_i ( instr_if.data_gnt & instr_if.data_req ),
.instr_if_data_gnt_i ( instr_if.data_gnt ),
.instr_if_data_rvalid_i ( instr_if.data_rvalid ),
.instr_if_data_rdata_i ( instr_if.data_rdata ),
@ -73,18 +73,14 @@ module lsu_tb;
.data_if_data_req_o ( slave.data_req ),
.data_if_data_we_o ( slave.data_we ),
.data_if_data_be_o ( slave.data_be ),
.data_if_data_gnt_i ( slave.data_gnt ),
// hack to not get a grant without a request
.data_if_data_gnt_i ( slave.data_req & slave.data_gnt ),
.data_if_data_rvalid_i ( slave.data_rvalid ),
.data_if_data_rdata_i ( slave.data_rdata ),
.lsu_exception_o ( lsu.exception )
);
// hack to not get a grant without a request
assign slave.data_gnt = slave.data_req & slave.data_gnt;
// hack to get a combinatorial path between ready and source valid
// assign lsu.source_valid = lsu.source_valid & lsu.ready;
initial begin
clk = 1'b0;
rst_ni = 1'b0;