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Updated Zcmp extension user guide and specification document (#1930)

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Rohan Arshid 2024-03-15 22:33:01 +05:00 • committed by GitHub
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2
docs/01_cva6_user/Programmer_View.rst
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@ -75,6 +75,7 @@ These extensions are available in CV32A60AX:
"RV32Zb* - Bit-Manipulation (Zba, Zbb, Zbc, Zbs)", "✔"
"RV32C - Compressed Instructions ", "✔"
"RV32Zcb - Code Size Reduction", "✔"
"RVZcmp - Code Size Reduction", ""
"RV32D - Double precision floating-point", ""
"RV32F - Single precision floating-point", ""
"RV32M - Integer Multiply/Divide", "✔"
@ -98,6 +99,7 @@ These extensions are available in CV32A60X:
"RV32Zb* - Bit-Manipulation (Zba, Zbb, Zbc, Zbs)", "✔"
"RV32C - Compressed Instructions ", "✔"
"RV32Zcb - Code Size Reduction", "✔"
"RVZcmp - Code Size Reduction", "✔"
"RV32D - Double precision floating-point", ""
"RV32F - Single precision floating-point", ""
"RV32M - Integer Multiply/Divide", "✔"

3
docs/01_cva6_user/RISCV_Instructions_RVZcmp.rst
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@ -25,7 +25,6 @@
:align: left
:header: "Configuration", "Implementation"
"CV32A60AX", "Implemented extension"
"CV32A60X", "Implemented extension"
**Note**: Zcmp is primarily targeted at embedded class CPUs due to implementation complexity. Additionally, it is not compatible with architecture class profiles.
@ -35,7 +34,7 @@ RVZcmp Code Size Reduction Instructions
Zcmp belongs to group of extensions called RISC-V Code Size Reduction Extension (Zc*). Zc* has become the superset of Standard C extension adding more 16-bit instructions to the ISA.
Zcmp includes 16-bit macro instructions, PUSH/POP and double move, which reuse the encoding for c.fsdsp instruction.
All the Zcmp instructions require at least standard C extension support as pre-requisite, along with Zca extension.
All the Zcmp instructions require at least C extension support with Zcd extension disabled as pre-requisite.
- **CM.PUSH**: Compressed Push

1
docs/01_cva6_user/index.rst
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@ -37,6 +37,7 @@ CVA6 User Manual
RV32A <RISCV_Instructions_RV32A>
RV32C <RISCV_Instructions_RV32C>
RV32Zcb <RISCV_Instructions_RV32ZCb>
RVZcmp <RISCV_Instructions_RVZcmp>
RVZba <RISCV_Instructions_RVZba>
RVZbb <RISCV_Instructions_RVZbb>
RVZbc <RISCV_Instructions_RVZbc>