Remove submodules, fix CI build

.gitlab-ci.yml

@@ -22,6 +22,7 @@ build-ci:
     - ci/make-tmp.sh
     - ci/install-fesvr.sh
     - ci/install-verilator.sh
+    - ci/build-riscv-tests.sh
   artifacts:
     paths:
       - tmp/
@@ -58,17 +59,17 @@ test_store_queue:
 test_core_asm:
   stage: test
   script:
-    - make build-tests
     - make build library=core_lib
     - make run-asm-tests library=core_lib
     - vcover-10.6 report run-asm-tests.ucdb
+  dependencies:
+    - build-ci
 
 test_core_asm_verilator:
   stage: test
   script:
-    - make build-tests
     - make verilate
-    - make run-asm-tests run-asm-tests-verilator
+    - make run-asm-tests-verilator
   dependencies:
     - build-ci
 
@@ -76,13 +77,14 @@ test_core_asm_verilator:
 .test_core_asm_rand:
   stage: test
   script:
-    - make build-tests
     - make build library=core_rand_lib
     # same as above but pass the rand_mem_if flag
     - make run-asm-tests library=core_rand_lib uvm-flags=+rand_mem_if
     - vcover-10.6 report run-asm-rand-tests.ucdb
+  dependencies:
+    - build-ci
 
-test_failed_tests:
+.test_failed_tests:
   stage: test
   script:
     - make build library=failed_tests_lib

Makefile

@@ -3,38 +3,46 @@
 # Description: Makefile for linting and testing Ariane.
 
 # compile everything in the following library
-library = work
+library ?= work
 # Top level module to compile
-top_level = core_tb
-test_top_level = core_tb
-
+top_level ?= core_tb
+test_top_level ?= core_tb
+# Maximum amount of cycles for a successful simulation run
+max_cycles ?= 10000000
+# Test case to run
+test_case ?= core_test
+# QuestaSim Version
+questa_version ?= -10.6b
+# preset which runs a single test
+riscv-test ?= rv64ui-p-add
+# Sources
 # Ariane PKG
-ariane_pkg = include/ariane_pkg.sv include/nbdcache_pkg.sv
+ariane_pkg := include/ariane_pkg.sv include/nbdcache_pkg.sv
 # utility modules
-util = $(wildcard src/util/*.svh) src/util/instruction_tracer_pkg.sv src/util/instruction_tracer_if.sv src/util/cluster_clock_gating.sv src/util/behav_sram.sv
+util := $(wildcard src/util/*.svh) src/util/instruction_tracer_pkg.sv src/util/instruction_tracer_if.sv src/util/cluster_clock_gating.sv src/util/behav_sram.sv
 # test targets
-tests = alu scoreboard fifo dcache_arbiter store_queue lsu core fetch_fifo
+tests := alu scoreboard fifo dcache_arbiter store_queue lsu core fetch_fifo
 # UVM agents
-agents = $(wildcard tb/agents/*/*.sv*)
+agents := $(wildcard tb/agents/*/*.sv*)
 # path to interfaces
-interfaces = $(wildcard include/*.svh)
+interfaces := $(wildcard include/*.svh)
 # UVM environments
-envs = $(wildcard tb/env/*/*.sv*)
+envs := $(wildcard tb/env/*/*.sv*)
 # UVM Sequences
-sequences =  $(wildcard tb/sequences/*/*.sv*)
+sequences := $(wildcard tb/sequences/*/*.sv*)
 # Test packages
-test_pkg = $(wildcard tb/test/*/*sequence_pkg.sv*) $(wildcard tb/test/*/*_pkg.sv*)
+test_pkg := $(wildcard tb/test/*/*sequence_pkg.sv*) $(wildcard tb/test/*/*_pkg.sv*)
 # DPI
-dpi = $(wildcard tb/dpi/*)
+dpi := $(wildcard tb/dpi/*)
 # this list contains the standalone components
-src = $(wildcard src/*.sv) $(wildcard tb/common/*.sv) $(wildcard src/axi2per/*.sv) $(wildcard src/axi_slice/*.sv) \
+src := $(wildcard src/*.sv) $(wildcard tb/common/*.sv) $(wildcard src/axi2per/*.sv) $(wildcard src/axi_slice/*.sv) \
 	  $(wildcard src/axi_node/*.sv) $(wildcard src/axi_mem_if/*.sv)
 # look for testbenches
-tbs = tb/alu_tb.sv tb/core_tb.sv tb/dcache_arbiter_tb.sv tb/store_queue_tb.sv tb/scoreboard_tb.sv tb/fifo_tb.sv
+tbs := tb/alu_tb.sv tb/core_tb.sv tb/dcache_arbiter_tb.sv tb/store_queue_tb.sv tb/scoreboard_tb.sv tb/fifo_tb.sv
 
 # RISCV-tests path
-riscv-test-dir = riscv-tests/isa
-riscv-tests =  rv64ui-p-add rv64ui-p-addi rv64ui-p-slli rv64ui-p-addiw rv64ui-p-addw rv64ui-p-and rv64ui-p-auipc 			 \
+riscv-test-dir := tmp/riscv-tests/isa
+riscv-tests := rv64ui-p-add rv64ui-p-addi rv64ui-p-slli rv64ui-p-addiw rv64ui-p-addw rv64ui-p-and rv64ui-p-auipc 			 \
 			   rv64ui-p-beq rv64ui-p-bge rv64ui-p-bgeu rv64ui-p-andi rv64ui-p-blt rv64ui-p-bltu rv64ui-p-bne                 \
 			   rv64ui-p-simple rv64ui-p-jal rv64ui-p-jalr rv64ui-p-or rv64ui-p-ori rv64ui-p-sub rv64ui-p-subw                \
 			   rv64ui-p-xor rv64ui-p-xori rv64ui-p-slliw rv64ui-p-sll rv64ui-p-slli rv64ui-p-sllw 							 \
@@ -57,28 +65,17 @@ riscv-tests =  rv64ui-p-add rv64ui-p-addi rv64ui-p-slli rv64ui-p-addiw rv64ui-p-
 			   rv64um-v-remu rv64um-v-mulw rv64um-v-divw rv64um-v-divuw rv64um-v-remw rv64um-v-remuw
 
 # failed test directory
-failed-tests =  $(wildcard failedtests/*.S)
-# preset which runs a single test
-riscv-test = rv64ui-p-add
+failed-tests := $(wildcard failedtests/*.S)
 # Search here for include files (e.g.: non-standalone components)
-incdir = ./includes
-# Maximum amount of cycles for a successful simulation run
-max_cycles = 10000000
-# Test case to run
-test_case = core_test
-# QuestaSim Version
-questa_version = -10.6b
-compile_flag = +cover=bcfst+/dut -incr -64 -nologo -quiet -suppress 13262 -permissive
-# Moore binary
-moore = ~fschuiki/bin/moore
-uvm-flags = +UVM_NO_RELNOTES
+incdir := ./includes
+# Compile and sim flags
+compile_flag += +cover=bcfst+/dut -incr -64 -nologo -quiet -suppress 13262 -permissive
+uvm-flags += +UVM_NO_RELNOTES
 # Iterate over all include directories and write them with +incdir+ prefixed
 # +incdir+ works for Verilator and QuestaSim
-list_incdir = $(foreach dir, ${incdir}, +incdir+$(dir))
+list_incdir := $(foreach dir, ${incdir}, +incdir+$(dir))
 
-# create library if it doesn't exist
-
-# # Build the TB and module using QuestaSim
+# Build the TB and module using QuestaSim
 build: $(library) $(library)/.build-agents $(library)/.build-interfaces $(library)/.build-components \
 		$(library)/.build-srcs $(library)/.build-tb
 		# Optimize top level
@@ -165,15 +162,6 @@ $(tests): build
 	-do "coverage save -onexit $@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" \
 	${library}.$@_tb_optimized
 
-build-moore:
-	[ ! -e .moore ] || rm .moore
-	$(foreach src_file, $(src), $(moore) compile $(src_file);)
-
-# build the RISC-V tests
-build-tests:
-	cd riscv-tests && autoconf && ./configure --prefix=/home/zarubaf/riscv && make isa -j8
-
-
 # User Verilator
 verilate:
 	verilator $(ariane_pkg) $(filter-out src/regfile.sv, $(wildcard src/*.sv)) src/util/behav_sram.sv src/axi_mem_if/axi2mem.sv tb/agents/axi_if/axi_if.sv \

ci/build-riscv-tests.sh

@@ -0,0 +1,23 @@
+#!/bin/sh
+set -e
+ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)
+cd $ROOT/tmp
+
+[ -d $ROOT/tmp/riscv-tests ] || git clone https://github.com/riscv/riscv-tests.git
+cd riscv-tests
+git checkout ffa920340430f62e767fb2397f4ee41ffaf441ce
+git submodule update --init --recursive
+autoconf
+mkdir -p build
+cd build
+../configure --prefix=$ROOT/tmp/riscv-tests/build
+make isa -j
+make install
+
+cd isa
+# generate hex files
+for f in $(ls | grep -v '\.[dump|hex]'); do
+    # elf2hex $f
+    echo "elf2hex $f > $f.hex"
+    elf2hex 8 16384 $f 2147483648 > $f.hex
+done

riscv-tests

@@ -1 +0,0 @@
-Subproject commit b253ea66b0f4e30f6ee7abf21a9f082e79224ade