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Flist.cv64a6_imafdc_sv39_gate and update LIB_VERILOG path (#804)

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Yannick Casamatta 2022-01-27 11:43:03 +01:00 • committed by GitHub
parent 9fda864835
commit bea9d5d1e6
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core/Flist.cv64a6_imafdc_sv39_gate
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@ -22,6 +22,6 @@ ${CVA6_REPO_DIR}/core/include/std_cache_pkg.sv
${CVA6_REPO_DIR}/core/include/axi_intf.sv
${CVA6_REPO_DIR}/core/include/instr_tracer_pkg.sv
${CVA6_REPO_DIR}/${LIB_VERILOG}
${LIB_VERILOG}
${CVA6_REPO_DIR}/pd/synth/ariane_synth_modified.v
${CVA6_REPO_DIR}/pd/synth/SyncSpRamBeNx64_1.sv