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✨ Implement privileged part of F-Extension
This commit is contained in:
Florian Zaruba
parent
3a9a0b7a58
commit
c762c5817a
8 changed files with 100 additions and 34 deletions
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@ -32,6 +32,13 @@ package riscv;
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XLEN_128 = 2'b11
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} xlen_t;
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typedef enum logic [1:0] {
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Off = 2'b00,
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Initial = 2'b01,
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Clean = 2'b10,
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Dirty = 2'b11
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} xs_t;
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typedef struct packed {
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logic sd; // signal dirty - read-only - hardwired zero
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logic [62:36] wpri4; // writes preserved reads ignored
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@ -44,8 +51,8 @@ package riscv;
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logic mxr; // make executable readable
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logic sum; // permit supervisor user memory access
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logic mprv; // modify privilege - privilege level for ld/st
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logic [1:0] xs; // extension register - hardwired to zero
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logic [1:0] fs; // extension register - hardwired to zero
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xs_t xs; // extension register - hardwired to zero
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xs_t fs; // floating point extension register
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priv_lvl_t mpp; // holds the previous privilege mode up to machine
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logic [1:0] wpri2; // writes preserved reads ignored
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logic spp; // holds the previous privilege mode up to supervisor
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@ -135,6 +135,7 @@ module ariane #(
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// --------------
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// CSR Commit
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logic csr_commit_commit_ex;
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logic dirty_fp_state;
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// LSU Commit
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logic lsu_commit_commit_ex;
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logic lsu_commit_ready_ex_commit;
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@ -154,6 +155,7 @@ module ariane #(
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// CSR <-> *
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// --------------
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logic [4:0] fflags_csr_commit;
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riscv::xs_t fs;
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logic [2:0] frm_csr_id_issue_ex;
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logic enable_translation_csr_ex;
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logic en_ld_st_translation_csr_ex;
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@ -255,6 +257,7 @@ module ariane #(
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.issue_instr_ack_i ( issue_instr_issue_id ),
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.priv_lvl_i ( priv_lvl ),
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.fs_i ( fs ),
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.frm_i ( frm_csr_id_issue_ex ),
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.debug_mode_i ( debug_mode_csr_id ),
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.tvm_i ( tvm_csr_id ),
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@ -415,8 +418,9 @@ module ariane #(
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// ---------
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commit_stage commit_stage_i (
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.halt_i ( halt_ctrl ),
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.flush_dcache_i ( dcache_flush_ctrl_cache ),
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.flush_dcache_i ( dcache_flush_ctrl_cache ),
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.exception_o ( ex_commit ),
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.dirty_fp_state_o ( dirty_fp_state ),
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.debug_mode_i ( debug_mode_csr_id ),
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.debug_req_i ( debug_req_i ),
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.single_step_i ( single_step_csr_commit ),
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@ -455,6 +459,7 @@ module ariane #(
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.ex_i ( ex_commit ),
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.csr_op_i ( csr_op_commit_csr ),
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.csr_write_fflags_i ( csr_write_fflags_commit_cs ),
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.dirty_fp_state_i ( dirty_fp_state ),
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.csr_addr_i ( csr_addr_ex_csr ),
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.csr_wdata_i ( csr_wdata_commit_csr ),
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.csr_rdata_o ( csr_rdata_csr_commit ),
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@ -465,6 +470,7 @@ module ariane #(
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.set_debug_pc_o ( set_debug_pc ),
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.trap_vector_base_o ( trap_vector_base_commit_pcgen ),
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.priv_lvl_o ( priv_lvl ),
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.fs_o ( fs ),
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.fflags_o ( fflags_csr_commit ),
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.frm_o ( frm_csr_id_issue_ex ),
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.ld_st_priv_lvl_o ( ld_st_priv_lvl_csr_ex ),
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@ -21,6 +21,7 @@ module commit_stage #(
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input logic halt_i, // request to halt the core
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input logic flush_dcache_i, // request to flush dcache -> also flush the pipeline
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output exception_t exception_o, // take exception to controller
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output logic dirty_fp_state_o, // mark the F state as dirty
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input logic debug_mode_i, // we are in debug mode
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input logic debug_req_i, // debug unit is requesting to enter debug mode
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input logic single_step_i, // we are in single step debug mode
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@ -55,6 +56,7 @@ module commit_stage #(
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assign waddr_o[1] = commit_instr_i[1].rd[4:0];
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assign pc_o = commit_instr_i[0].pc;
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assign dirty_fp_state_o = |we_fpr_o;
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// -------------------
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// Commit Instruction
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@ -69,7 +71,6 @@ module commit_stage #(
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we_gpr_o[0] = 1'b0;
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we_gpr_o[1] = 1'b0;
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we_fpr_o = '{default: 1'b0};
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commit_lsu_o = 1'b0;
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commit_csr_o = 1'b0;
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wdata_o[0] = commit_instr_i[0].result;
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@ -21,7 +21,6 @@ module csr_regfile #(
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input logic clk_i, // Clock
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input logic rst_ni, // Asynchronous reset active low
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input logic time_irq_i, // Timer threw a interrupt
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// send a flush request out if a CSR with a side effect has changed (e.g. written)
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output logic flush_o,
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output logic halt_csr_o, // halt requested
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@ -39,6 +38,7 @@ module csr_regfile #(
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input logic [11:0] csr_addr_i, // Address of the register to read/write
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input logic [63:0] csr_wdata_i, // Write data in
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output logic [63:0] csr_rdata_o, // Read data out
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input logic dirty_fp_state_i, // Mark the FP sate as dirty
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input logic csr_write_fflags_i, // Write fflags register e.g.: we are retiring a floating point instruction
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input logic [63:0] pc_i, // PC of instruction accessing the CSR
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output exception_t csr_exception_o, // attempts to access a CSR without appropriate privilege
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@ -50,6 +50,7 @@ module csr_regfile #(
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output logic [63:0] trap_vector_base_o, // Output base of exception vector, correct CSR is output (mtvec, stvec)
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output riscv::priv_lvl_t priv_lvl_o, // Current privilege level the CPU is in
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// FPU
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output riscv::xs_t fs_o, // Floating point extension status
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output logic [4:0] fflags_o, // Floating-Point Accured Exceptions
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output logic [2:0] frm_o, // Floating-Point Dynamic Rounding Mode
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// MMU
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@ -91,12 +92,14 @@ module csr_regfile #(
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logic mret; // return from M-mode exception
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logic sret; // return from S-mode exception
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logic dret; // return from debug mode
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// CSR write causes us to mark the FPU state as dirty
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logic dirty_fp_state_csr;
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riscv::csr_t csr_addr;
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// ----------------
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// Assignments
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// ----------------
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assign csr_addr = riscv::csr_t'(csr_addr_i);
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assign fs_o = mstatus_q.fs;
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// ----------------
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// CSR Registers
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// ----------------
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@ -153,9 +156,27 @@ module csr_regfile #(
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if (csr_read) begin
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case (csr_addr.address)
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riscv::CSR_FFLAGS: csr_rdata = {59'b0, fcsr_q.fflags};
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riscv::CSR_FRM: csr_rdata = {61'b0, fcsr_q.frm};
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riscv::CSR_FCSR: csr_rdata = {32'b0, fcsr_q};
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riscv::CSR_FFLAGS: begin
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if (mstatus_q.fs == riscv::Off) begin
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read_access_exception = 1'b1;
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end else begin
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csr_rdata = {59'b0, fcsr_q.fflags};
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end
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end
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riscv::CSR_FRM: begin
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if (mstatus_q.fs == riscv::Off) begin
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read_access_exception = 1'b1;
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end else begin
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csr_rdata = {61'b0, fcsr_q.frm};
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end
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end
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riscv::CSR_FCSR: begin
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if (mstatus_q.fs == riscv::Off) begin
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read_access_exception = 1'b1;
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end else begin
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csr_rdata = {32'b0, fcsr_q};
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end
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end
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// debug registers
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riscv::CSR_DCSR: csr_rdata = {32'b0, dcsr_q};
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riscv::CSR_DPC: csr_rdata = dpc_q;
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@ -287,25 +308,40 @@ module csr_regfile #(
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stval_d = stval_q;
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satp_d = satp_q;
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en_ld_st_translation_d = en_ld_st_translation_q;
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dirty_fp_state_csr = 1'b0;
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// check for correct access rights and that we are writing
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if (csr_we) begin
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case (csr_addr.address)
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// Floating-Point
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riscv::CSR_FFLAGS: begin
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fcsr_d.fflags = csr_wdata[4:0];
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// this instruction has side-effects
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flush_o = 1'b1;
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if (mstatus_q.fs == riscv::Off) begin
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update_access_exception = 1'b1;
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end else begin
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dirty_fp_state_csr = 1'b1;
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fcsr_d.fflags = csr_wdata[4:0];
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// this instruction has side-effects
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flush_o = 1'b1;
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end
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end
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riscv::CSR_FRM: begin
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fcsr_d.frm = csr_wdata[2:0];
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// this instruction has side-effects
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flush_o = 1'b1;
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if (mstatus_q.fs == riscv::Off) begin
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update_access_exception = 1'b1;
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end else begin
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dirty_fp_state_csr = 1'b1;
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fcsr_d.frm = csr_wdata[2:0];
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// this instruction has side-effects
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flush_o = 1'b1;
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end
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end
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riscv::CSR_FCSR: begin
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fcsr_d[7:0] = csr_wdata[7:0]; // ignore writes to reserved space
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// this instruction has side-effects
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flush_o = 1'b1;
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if (mstatus_q.fs == riscv::Off) begin
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update_access_exception = 1'b1;
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end else begin
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dirty_fp_state_csr = 1'b1;
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fcsr_d[7:0] = csr_wdata[7:0]; // ignore writes to reserved space
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// this instruction has side-effects
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flush_o = 1'b1;
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end
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end
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// debug CSR
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riscv::CSR_DCSR: begin
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@ -330,10 +366,13 @@ module csr_regfile #(
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// also hardwire the registers for sstatus
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mstatus_d.sxl = riscv::XLEN_64;
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mstatus_d.uxl = riscv::XLEN_64;
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// hardwired zero registers
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mstatus_d.sd = 1'b0;
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mstatus_d.xs = 2'b0;
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mstatus_d.fs = 2'b0;
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// hardwired extension registers
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mstatus_d.sd = (&mstatus_q.xs) | (&mstatus_q.fs);
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mstatus_d.xs = riscv::Off;
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// hardwire to zero if floating point extension is not present
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if (!FP_PRESENT) begin
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mstatus_d.fs = riscv::Off;
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end
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mstatus_d.upie = 1'b0;
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mstatus_d.uie = 1'b0;
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// not all fields of mstatus can be written
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@ -390,9 +429,11 @@ module csr_regfile #(
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mstatus_d.sxl = riscv::XLEN_64;
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mstatus_d.uxl = riscv::XLEN_64;
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// hardwired zero registers
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mstatus_d.sd = 1'b0;
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mstatus_d.xs = 2'b0;
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mstatus_d.fs = 2'b0;
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mstatus_d.sd = (&mstatus_q.xs) | (&mstatus_q.fs);
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mstatus_d.xs = riscv::Off;
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if (!FP_PRESENT) begin
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mstatus_d.fs = riscv::Off;
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end
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mstatus_d.upie = 1'b0;
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mstatus_d.uie = 1'b0;
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// this register has side-effects on other registers, flush the pipeline
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@ -451,6 +492,11 @@ module csr_regfile #(
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endcase
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end
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// mark the floating point extension register as dirty
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if (FP_PRESENT && (dirty_fp_state_csr || dirty_fp_state_i)) begin
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mstatus_d.fs = riscv::Dirty;
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end
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// write the floating point status register
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if (csr_write_fflags_i)
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fcsr_d.fflags = csr_wdata_i[4:0] | fcsr_q.fflags;
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@ -30,6 +30,7 @@ module decoder (
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// From CSR
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input riscv::priv_lvl_t priv_lvl_i, // current privilege level
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input logic debug_mode_i, // we are in debug mode
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input riscv::xs_t fs_i, // floating point extension status
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input logic [2:0] frm_i, // floating-point dynamic rounding mode
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input logic tvm_i, // trap virtual memory
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input logic tw_i, // timeout wait
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@ -244,7 +245,8 @@ module decoder (
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// Vectorial Floating-Point Reg-Reg Operations
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// --------------------------------------------
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if (instr.rvftype.funct2 == 2'b10) begin // Prefix 10 for all Xfvec ops
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if (FP_PRESENT & XFVEC) begin // only generate decoder if FP extensions are enabled (static)
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// only generate decoder if FP extensions are enabled (static)
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if (FP_PRESENT && XFVEC && fs_i != riscv::Off) begin
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automatic logic allow_replication; // control honoring of replication flag
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instruction_o.fu = FPU_VEC; // Same unit, but sets 'vectorial' signal
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@ -618,7 +620,7 @@ module decoder (
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// Floating-Point Load/store
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// --------------------------------
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riscv::OpcodeStoreFp: begin
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if (FP_PRESENT) begin // only generate decoder if FP extensions are enabled (static)
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if (FP_PRESENT && fs_i != riscv::Off) begin // only generate decoder if FP extensions are enabled (static)
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instruction_o.fu = STORE;
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imm_select = SIMM;
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instruction_o.rs1 = instr.stype.rs1;
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@ -641,7 +643,7 @@ module decoder (
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end
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riscv::OpcodeLoadFp: begin
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if (FP_PRESENT) begin // only generate decoder if FP extensions are enabled (static)
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if (FP_PRESENT && fs_i != riscv::Off) begin // only generate decoder if FP extensions are enabled (static)
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instruction_o.fu = LOAD;
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imm_select = IIMM;
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instruction_o.rs1 = instr.itype.rs1;
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@ -670,7 +672,7 @@ module decoder (
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riscv::OpcodeMsub,
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riscv::OpcodeNmsub,
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riscv::OpcodeNmadd: begin
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if (FP_PRESENT) begin // only generate decoder if FP extensions are enabled (static)
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if (FP_PRESENT && fs_i != riscv::Off) begin // only generate decoder if FP extensions are enabled (static)
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instruction_o.fu = FPU;
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instruction_o.rs1 = instr.r4type.rs1;
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instruction_o.rs2 = instr.r4type.rs2;
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@ -723,7 +725,7 @@ module decoder (
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end
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riscv::OpcodeOpFp: begin
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if (FP_PRESENT) begin // only generate decoder if FP extensions are enabled (static)
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if (FP_PRESENT && fs_i != riscv::Off) begin // only generate decoder if FP extensions are enabled (static)
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instruction_o.fu = FPU;
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instruction_o.rs1 = instr.rftype.rs1;
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instruction_o.rs2 = instr.rftype.rs2;
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@ -122,7 +122,8 @@ module ex_stage #(
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// Branch Engine
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// --------------------
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branch_unit branch_unit_i (
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.fu_valid_i ( alu_valid_i || lsu_valid_i || csr_valid_i || mult_valid_i), // any functional unit is valid, check that there is no accidental mis-predict
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// any functional unit is valid, check that there is no accidental mis-predict
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.fu_valid_i ( alu_valid_i || lsu_valid_i || csr_valid_i || mult_valid_i || fpu_valid_i ),
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.branch_comp_res_i ( alu_branch_res ),
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.*
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);
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@ -139,7 +140,7 @@ module ex_stage #(
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// FPU
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// ----------------
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generate
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if( FP_PRESENT ) begin : fpu_gen
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if (FP_PRESENT) begin : fpu_gen
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fpu_wrap fpu_i (
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.operand_c_i ( imm_i ),
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.result_o ( fpu_result_o ),
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@ -32,6 +32,7 @@ module id_stage (
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input logic issue_instr_ack_i, // issue stage acknowledged sampling of instructions
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// from CSR file
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input riscv::priv_lvl_t priv_lvl_i, // current privilege level
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input riscv::xs_t fs_i, // floating point extension status
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input logic [2:0] frm_i, // floating-point dynamic rounding mode
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input logic debug_mode_i, // we are in debug mode
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@ -92,6 +93,8 @@ module id_stage (
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.ex_i ( fetch_entry.ex ),
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.instruction_o ( decoded_instruction ),
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.is_control_flow_instr_o ( is_control_flow_instr ),
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.fs_i,
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.frm_i,
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.*
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);
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@ -233,7 +233,7 @@ module issue_read_operands #(
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// use the zimm as operand a
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if (issue_instr_i.use_zimm) begin
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// zero extend operand a
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operand_a_n = {52'b0, issue_instr_i.rs1};
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operand_a_n = {52'b0, issue_instr_i.rs1[4:0]};
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end
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// or is it an immediate (including PC), this is not the case for a store and control flow instructions
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if (issue_instr_i.use_imm && (issue_instr_i.fu != STORE) && (issue_instr_i.fu != CTRL_FLOW)) begin
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